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[File Operate] 我的SDRAM资料收藏

Description: RAM（Random Access Memory）随机存取存储器对于系统性能的影响是每个PC用户都非常清楚的，所以很多朋友趁着现在的内存价格很低纷纷扩容了内存，希望借此来得到更高的性能。不过现在市场是多种内存类型并存的，SDRAM、DDR SDRAM、RDRAM等等，如果你使用的还是非常古老的系统，可能还需要EDO DRAM、FP DRAM（块页）等现在不是很常见的内存-RAM (Random Access Memory) random access memory system performance for the impact of each PC users are very clear, so many of my friends now take advantage of the low prices have memory expansion memory, with a view to get higher performance. But now the market is a mixture of both types of memory, SDRAM, DDR SDRAM, RDRAM, etc. If you use or the very old, may also need to EDO DRAM, FP DRAM (block pages) is now is not very common memory
Platform: | Size: 775168 | Author: 周卫成 | Hits:

[SCM] 1335c51

Description: SED1335驱动320x240图形液晶驱动演示程序320x240液晶模块配用sed1335驱动接口板，sed1335驱动接口板上配用32K ram-SED1335 drive 320x240 graphics LCD driver demo program 320x240 LCD module using block sed1335 driven interface board, the board sed1335 driven interface using 32K ram
Platform: | Size: 15360 | Author: 江川 | Hits:

[ARM-PowerPC-ColdFire-MIPS] d169_dma

Description: D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger Description A 32 byte block from 220h-240h is transfered to 240h-260h using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to inital software setting because DMA transfer mode 5 is used. P1.0 is toggled durring DMA transfer only for demonstration purposes. ** RAM location 0x220 - 0x260 used - always make sure no compiler conflict ** ACLK= n/a, MCLK= SMCLK= default DCO ~ 800k-D169 Demo- DMA0 Repeated Burst to-from RAM, Software Trigger Description A 32 byte block from 220h-240h is transfered to 240h-260h using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to inital software setting because DMA transfer mode 5 is used. P1.0 is toggled durring DMA transfer only for demonstration purposes. ** RAM location 0x220- 0x260 used- always make sure no compiler conflict** ACLK= n/a, MCLK= SMCLK= default DCO ~ 800k
Platform: | Size: 7168 | Author: 梁武潔 | Hits:

[VHDL-FPGA-Verilog] BlockRAM

Description: xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
Platform: | Size: 2048 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] XAPP204

Description: Using Block RAM for High-Performance Read.Write Cams
Platform: | Size: 55296 | Author: ryan | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[Software Engineering] newcode

Description: ram block discription ,which are fullfill all kind of fuction that you need-ram block discription, which are fullfill all kind of fuction that you need
Platform: | Size: 4085760 | Author: wang | Hits:

[Software Engineering] RAM

Description: 使用ISE的XST综合，综合结果使用了Block RAM，当然有时对于用到的容量很小的RAM，我们并不需要其使用Block RAM，那么只要稍微修改一下就可以综合成Distribute RAM-The use of ISE s XST synthesis, the combined result of the use of the Block RAM, it is our expectation. Of course, sometimes the capacity to use a very small RAM, we do not need its use Block RAM, as long as a slight change it can be integrated into Distribute RAM
Platform: | Size: 7168 | Author: 刘珊 | Hits:

[VHDL-FPGA-Verilog] TechXclusives-ReconfiguringBlockRAMs

Description: Xilinx FPGA block RAM reconfig via JTAG
Platform: | Size: 104448 | Author: Kraja | Hits:

[VHDL-FPGA-Verilog] TechXclusives-UsingLeftoverMultipliersandBlockRAM

Description: Xilinx FPGA using leftover multipliers and block RAM
Platform: | Size: 62464 | Author: Kraja | Hits:

[Software Engineering] spartan6_fpga_blockram_user_guide

Description: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Platform: | Size: 376832 | Author: james | Hits:

[Windows Develop] read

Description: 在FPGA内部实现RAM块中数据的读出，简单方便。-Internal implementation in FPGA block RAM read data
Platform: | Size: 582656 | Author: 庞利会 | Hits:

[Other] dualportram_vhdl

Description: 采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化-VHDL hardware description language using the dual-caliber RAM block memory initialization
Platform: | Size: 2048 | Author: sharbel | Hits:

[VHDL-FPGA-Verilog] using_the_block_RAM_in_Spartan-3_FPGA

Description: Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
Platform: | Size: 32768 | Author: lishiwei | Hits:

[VHDL-FPGA-Verilog] Ram-block-code

Description: It is a VHDL code for Block RAM
Platform: | Size: 1024 | Author: Umair | Hits:

[VHDL-FPGA-Verilog] 256.16-RAM

Description: VHDL语言编写，实现256×16RAM块功能，稍加修改即可改变RAM块的容量-VHDL language, achieving 256 ×16RAM block .A little change can change the capacity of the block RAM
Platform: | Size: 266240 | Author: 王建伟 | Hits:

[VHDL-FPGA-Verilog] RAM_BLOCK

Description: Ram block code in Verilog
Platform: | Size: 25600 | Author: M. Usman | Hits:

[Industry research] Using-the-Virtex-Block-SelectRAMP

Description: The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, or a write port, and each port can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs.-The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, or a write port, and each port can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs.
Platform: | Size: 66560 | Author: asura | Hits:

[VHDL-FPGA-Verilog] BlockRam

Description: 块状ram使用实例，实现深度和宽度可调的FIFO，buffer。-The block ram instance, depth and width adjustable FIFO, buffer.
Platform: | Size: 2963456 | Author: zwl6600233 | Hits:

[Other] Block_RAM

Description: ditributed ram in fpga and block ram in fpga
Platform: | Size: 1170432 | Author: ghanbari1995 | Hits:
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