ref-ualaw A rate/u rate compression and decompress

Title: ref-ualaw

Category:
VHDL-FPGA-Verilog
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116.87kb
Update:
2008-10-13
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1204424

Description: A rate/u rate compression and decompression of the IP core,. By AHDL# languages, and the Quartus II MaxplusII use, the source code encryption.

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