RS422_receiver verilog--A UART Receiver 16 clock - CodeBus

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VHDL-FPGA-Verilog

Title: RS422_receiver

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
ltmtt

Description: verilog--A UART Receiver 16 clock

Downloaders recently: [More information of uploader ltmtt]

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RS422_receiver.v

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