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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: counter Download
 Description: Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
 Downloaders recently: [More information of uploader ok-double]
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File list (Check if you may need any files): 
频率计(测周法)
..............\clk2.bsf
..............\clkgen.bsf
..............\clkgen.v
..............\control.v
..............\Counter.bsf
..............\Counter.v
..............\db
..............\..\add_sub_0fc.tdf
..............\..\add_sub_1fc.tdf
..............\..\add_sub_2fc.tdf
..............\..\add_sub_3dc.tdf
..............\..\add_sub_4dc.tdf
..............\..\add_sub_5dc.tdf
..............\..\add_sub_6dc.tdf
..............\..\add_sub_7dc.tdf
..............\..\add_sub_8dc.tdf
..............\..\add_sub_9dc.tdf
..............\..\add_sub_adc.tdf
..............\..\add_sub_bdc.tdf
..............\..\add_sub_i4h.tdf
..............\..\add_sub_j4h.tdf
..............\..\add_sub_jec.tdf
..............\..\add_sub_kec.tdf
..............\..\add_sub_lec.tdf
..............\..\add_sub_m4h.tdf
..............\..\add_sub_mac.tdf
..............\..\add_sub_mec.tdf
..............\..\add_sub_n4h.tdf
..............\..\add_sub_nac.tdf
..............\..\add_sub_nec.tdf
..............\..\add_sub_oec.tdf
..............\..\add_sub_pec.tdf
..............\..\add_sub_q4h.tdf
..............\..\add_sub_qec.tdf
..............\..\add_sub_rec.tdf
..............\..\add_sub_sec.tdf
..............\..\add_sub_tec.tdf
..............\..\add_sub_uec.tdf
..............\..\add_sub_vec.tdf
..............\..\alt_u_div_2ue.tdf
..............\..\alt_u_div_4ue.tdf
..............\..\FreCounter.asm.qmsg
..............\..\FreCounter.cbx.xml
..............\..\FreCounter.cmp.cdb
..............\..\FreCounter.cmp.hdb
..............\..\FreCounter.cmp.kpt
..............\..\FreCounter.cmp.logdb
..............\..\FreCounter.cmp.rdb
..............\..\FreCounter.cmp.tdb
..............\..\FreCounter.cmp0.ddb
..............\..\FreCounter.dbp
..............\..\FreCounter.db_info
..............\..\FreCounter.eco.cdb
..............\..\FreCounter.eds_overflow
..............\..\FreCounter.fit.qmsg
..............\..\FreCounter.hier_info
..............\..\FreCounter.hif
..............\..\FreCounter.map.cdb
..............\..\FreCounter.map.hdb
..............\..\FreCounter.map.logdb
..............\..\FreCounter.map.qmsg
..............\..\FreCounter.pre_map.cdb
..............\..\FreCounter.pre_map.hdb
..............\..\FreCounter.psp
..............\..\FreCounter.rtlv.hdb
..............\..\FreCounter.rtlv_sg.cdb
..............\..\FreCounter.rtlv_sg_swap.cdb
..............\..\FreCounter.sgdiff.cdb
..............\..\FreCounter.sgdiff.hdb
..............\..\FreCounter.signalprobe.cdb
..............\..\FreCounter.sim.hdb
..............\..\FreCounter.sim.qmsg
..............\..\FreCounter.sim.rdb
..............\..\FreCounter.sim.vwf
..............\..\FreCounter.sld_design_entry.sci
..............\..\FreCounter.sld_design_entry_dsc.sci
..............\..\FreCounter.syn_hier_info
..............\..\FreCounter.tan.qmsg
..............\..\lpm_divide_d8m.tdf
..............\..\lpm_divide_e8m.tdf
..............\..\sign_div_unsign_9nh.tdf
..............\..\sign_div_unsign_anh.tdf
..............\..\wed.zsf
..............\D_ff.bsf
..............\D_ff.v
..............\d_latch.bsf
..............\d_latch.v
..............\FreCounter.asm.rpt
..............\FreCounter.cdf
..............\FreCounter.done
..............\FreCounter.fit.rpt
..............\FreCounter.fit.smsg
..............\FreCounter.fit.summary
..............\FreCounter.flow.rpt
..............\FreCounter.gdf
..............\FreCounter.map.rpt
..............\FreCounter.map.summary
..............\FreCounter.pin
..............\FreCounter.pof

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