Description: VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
- [abc] - : In the FPGA to achieve the high-freque
- [123] - : Digital down-conversion software radio
- [bunchcombinechange] - Verilog source code, realize SERDES, lea
- [Ali_M3328C] - ? ? ? ??犓? ? ?? ?? ? ??? ???? ? ? ??? ?
- [FPGA] - FPGA
- [up_convert] - vhdl hardware design on the realization
- [verilog_FPGA_DDC] - This a verilog HDL used to achieve the r
- [fir_dec3] - FIR decimation filter, extraction coeffi
- [DDC] - Multi-channel digital down conversion of
File list (Check if you may need any files):
project_UHF_ddc
...............\cic_40.asy
...............\cic_40.edn
...............\cic_40.ngo
...............\cic_40.sym
...............\cic_40.v
...............\cic_40.veo
...............\cic_40.vhd
...............\cic_40.vho
...............\cic_40.xco
...............\cic_40_flist.txt
...............\cic_40_readme.txt
...............\CIC_C_fir.coe
...............\CIC_C_fir.coe.bak
...............\COEF_BUFFER.mif
...............\ddc_lpf.ngc
...............\ddc_lpf.ngr
...............\ddc_lpf.vhd
...............\ddc_lpf_summary.html
...............\dds_214.asy
...............\dds_214.edn
...............\dds_214.ngo
...............\dds_214.sym
...............\dds_214.v
...............\dds_214.veo
...............\dds_214.vhd
...............\dds_214.vho
...............\dds_214.xco
...............\dds_214_flist.txt
...............\dds_214_readme.txt
...............\dds_214_SINCOS_TABLE_TRIG_ROM.mif
...............\hc_fir.asy
...............\hc_fir.edn
...............\hc_fir.mif
...............\hc_fir.ngo
...............\hc_fir.sym
...............\hc_fir.v
...............\hc_fir.veo
...............\hc_fir.vhd
...............\hc_fir.vho
...............\hc_fir.xco
...............\hc_fir_flist.txt
...............\hc_fir_readme.txt
...............\lpf_fir.asy
...............\lpf_fir.coe
...............\lpf_fir.coe.bak
...............\lpf_fir.edn
...............\lpf_fir.mif
...............\lpf_fir.ngo
...............\lpf_fir.sym
...............\lpf_fir.v
...............\lpf_fir.veo
...............\lpf_fir.vhd
...............\lpf_fir.vho
...............\lpf_fir.xco
...............\lpf_fir_flist.txt
...............\lpf_fir_readme.txt
...............\multiplier_14.asy
...............\multiplier_14.edn
...............\multiplier_14.ngo
...............\multiplier_14.sym
...............\multiplier_14.v
...............\multiplier_14.veo
...............\multiplier_14.vhd
...............\multiplier_14.vho
...............\multiplier_14.xco
...............\multiplier_14_flist.txt
...............\multiplier_14_mult_gen_v9_0_xst_1.ngc
...............\multiplier_14_readme.txt
...............\pepExtractor.prj
...............\project_UHF_ddc.ise
...............\project_UHF_ddc.ise_ISE_Backup
...............\project_UHF_ddc.ntrc_log
...............\templates
...............\.........\coregen.xml
...............\transcript
...............\UHF-DDC设计参数.doc
...............\UHF_ddc.cmd_log
...............\UHF_ddc.lso
...............\UHF_ddc.ngc
...............\UHF_ddc.ngr
...............\UHF_ddc.prj
...............\UHF_ddc.stx
...............\UHF_ddc.syr
...............\UHF_ddc.udo
...............\UHF_ddc.vhd
...............\UHF_ddc.xst
...............\UHF_ddc_summary.html
...............\UHF_ddc_tb.vhd
...............\UHF_ddc_tb_vhd.fdo
...............\UHF_ddc_tb_vhd.udo
...............\vsim.wlf
...............\work
...............\....\cic_40
...............\....\......\verilog.asm
...............\....\......\_primary.dat
...............\....\......\_primary.vhd
...............\....\ddc_lpf
...............\....\.......\behavioral.asm
...............\....\.......\behavioral.dat
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