clock_divider Generate arbitrary decimal divider p

Title: clock_divider

Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
23kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
xxy1984

Description: Generate arbitrary decimal divider principle, and detailed description of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL examples)

Downloaders recently: [More information of uploader xxy1984]

To Search: odd frequency divider with vhdl frequency divider divider

[feizhenshu] - non-integer frequency divider coefficien
[Verilog_FPGA_fp] - using Verilog FPGA-based Universal Frequ
[my_design_frequency] - in digital circuits, and often the need
[VHDL_FOR_DIV] - clearly described how to use VHDL design
[DDS1] - DDS signal generator, can produce a vari
[div] - VHDL arbitrary integer frequency procedu
[DDS_vhdl] - The realization of arbitrary fractional-
[huaweixiaoshufenpin] - Huawei s patented fractional-N contents
[baweichufaqi] - Introduced the use of VHDL to achieve ei
[shukongfenpinqi] - NC divider d esign of its function is wh

File list (Check if you may need any files):

任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子).pdf

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net