Description: Divider in the figure occupies a very important position in detail in this paper to resolve the parity sub-frequency algorithm! As well as fractional-N algorithm! Are a valuable summary, there are examples for reference!
- [fen] - Verilog, 4,5 dividers, five dividers rat
- [9] - This article describes two kinds of sub-
- [NdotXfd] - Can be arbitrary, a fractional-N, in the
- [VHDL] - Realize arbitrary fractional-N of the VH
- [clock_divider] - Generate arbitrary decimal divider princ
- [fenping] - Document listed a number of crossovers,
- [6.5fenpin] - fen pin qi
- [FPQ] - VHDL simulation of the realization of cr
- [divider] - Divider design includes an odd divider,
File list (Check if you may need any files):
分频器.doc
分频器.txt
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