wtut_ver verilog HDL language digital stopwatch, s - CodeBus

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Title: wtut_ver

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
25.88kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
estony

Description: verilog HDL language digital stopwatch, simulation has already been adopted, for reference

Downloaders recently: [More information of uploader estony]

To Search: wtut_ver.zip wtut_ver stopwatch digital vhdl

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