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[VHDL-FPGA-Verilog] VGA_LCD_IP

Description: vga ipcore的verilog代码
Platform: | Size: 495616 | Author: | Hits:

[VHDL-FPGA-Verilog] IPcore

Description: 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
Platform: | Size: 1486848 | Author: wzk | Hits:

[VHDL-FPGA-Verilog] ddc_FPGA

Description: 简要介绍了数字下变频的设计，通过采用xilinx的ise软件，ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
Platform: | Size: 2578432 | Author: 望天 | Hits:

[Software Engineering] ipcore

Description: XILINX公司ISE自带的IP核，功能介绍，如何使用这些IP核来加快你的开发。-IP release note guide
Platform: | Size: 162816 | Author: 老刘 | Hits:

[Other] EtherCAT_IPCore_Xilinx_V2_02a_Datasheet_all_v2i2i1

Description:
Platform: | Size: 3204096 | Author: Homer | Hits:

[VHDL-FPGA-Verilog] standard_sim_tb

Description: xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise
Platform: | Size: 13312 | Author: zhou | Hits:

[VHDL-FPGA-Verilog] hwitl_sim

Description: xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.
Platform: | Size: 99328 | Author: zhou | Hits:

[VHDL-FPGA-Verilog] ctc_advanced_sim_tb

Description: xilinx CTC IPcore 误码率测试-xilinx CTC IPcore Bit Error Rate Test
Platform: | Size: 216064 | Author: zhou | Hits:

[ARM-PowerPC-ColdFire-MIPS] 2440Program

Description: ARM 2440的操作系统与IPcore 设计-ARM 2440 operation system and IPcore
Platform: | Size: 496640 | Author: 李江 | Hits:

[Embeded Linux] Xilinx

Description: Xilinx12.3和12.4 license 加强版支持更多ipcore 以及modelsim编译ise 库的方法说明-Xilinx12.3 and 12.4 license as well as enhanced support for more ipcore modelsim compile ise description of the ways library
Platform: | Size: 1235968 | Author: 王垚 | Hits:

[VHDL-FPGA-Verilog] ddr2_mem

Description: DDR2 xilinx ipcore 头文件 可以进行读写DDR2操作的接口! 读写时注意 按照时序控制进行！-DDR2 xilinx top file， you can read or write DDR2 interface。 attention：please control it ！
Platform: | Size: 6144 | Author: yan | Hits:

[Other Embeded program] Xilinx_DDR2_IP_TEST

Description: 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed description. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
Platform: | Size: 503808 | Author: 刘明 | Hits:

[VHDL-FPGA-Verilog] FIFO_TEST

Description: XILINX FIFO IP核测试程序，已经通过测试，方便可用-XILINX FIFO IPcore testbench
Platform: | Size: 413696 | Author: 飞草 | Hits:

[VHDL-FPGA-Verilog] microblaze_GPIO

Description: 基于xilinx 的软核microblaze的GPIO IP核程序(GPIO IPcore program for soft core MicroBlaze based on Xilinx)
Platform: | Size: 63939584 | Author: kristen123 | Hits:

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