Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - xilinx

Search list

[Embeded-SCM Develop] Xilinx_9

Description: Xilinx ISE 官方源代码盘第九章-Xilinx ISE official source was the ninth chapter
Platform: | Size: 613376 | Author: guorui | Hits:

[Embeded-SCM Develop] Xilinx_10

Description: Xilinx ISE 官方源代码盘第十章-Xilinx ISE official source was the 10th chapter
Platform: | Size: 7497728 | Author: guorui | Hits:

[Other] XilinxJTAF

Description: XilinxJTAG.rar xilinx CPLD,FPGA的JTAG口使用说明.-XilinxJTAG.rar Xilinx CPLD, FPGA JTAG I use.
Platform: | Size: 431104 | Author: | Hits:

[VHDL-FPGA-Verilog] userbscan

Description: xilinx FPGA上使用jtag接口作为用户IO的源码。支持任意位宽度。-Xilinx FPGAs use JTAG interface as user IO source. Support for arbitrary bit width.
Platform: | Size: 1024 | Author: 尹成科 | Hits:

[SCM] 7seg_led

Description: 使用xilinx公司的FPGA实现了七段码的定时器时钟程序-use of the Xilinx FPGA in paragraph 107 of the Code timer clock procedures
Platform: | Size: 222208 | Author: 张天齐 | Hits:

[Other] 321434354366547

Description: Xilinx FPGA最小系统板设计-Xilinx FPGA minimum system board design
Platform: | Size: 498688 | Author: lele | Hits:

[DSP program] 11lab01

Description: 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（1）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (1)
Platform: | Size: 568320 | Author: zhangxing | Hits:

[matlab] 13lab03

Description: 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3)
Platform: | Size: 308224 | Author: zhangxing | Hits:

[VHDL-FPGA-Verilog] Push_Boxes

Description: 在Xilinx环境下编写的vhdl程序，实现推箱子的游戏任务，界面很漂亮。-Xilinx environment in the preparation of the VHDL program, realized the game viewing tasks, the interface is very beautiful.
Platform: | Size: 6144 | Author: 吴倩茜 | Hits:

[VHDL-FPGA-Verilog] addsub_core_

Description: hdl的8051核，不知道好不好用大家试试吧。xilinx公司的核-HDL 8051 nuclear, we know that is really useful to try it. Xilinx's nuclear
Platform: | Size: 1024 | Author: 徐泯 | Hits:

[Windows Develop] xapp195

Description: signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
Platform: | Size: 7168 | Author: ldy | Hits:

[VHDL-FPGA-Verilog] clockbyvhdl

Description: 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
Platform: | Size: 27648 | Author: 马永涛 | Hits:

[VHDL-FPGA-Verilog] pwmvhdl

Description: 一个在xilinx的ise环境下编译仿真成功的pWM程序。-one of the Xilinx environment ideally compiler pWM success of the simulation procedures.
Platform: | Size: 136192 | Author: 马永涛 | Hits:

[VHDL-FPGA-Verilog] keybyise

Description: 一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。-a company embarks on the environment and ideally compile successful simulation keyboard operations.
Platform: | Size: 97280 | Author: 马永涛 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Platform: | Size: 23552 | Author: 冯伟 | Hits:

[Other Embeded program] Memec_3SLC_Schematic_Rev1p2

Description: Xilinx 的Spartan3的原理图,老外画的,很值得研究 .-Xilinx Spartan3 the schematics, pictures of foreigners, is worth studies.
Platform: | Size: 219136 | Author: wpb3dm | Hits:

[SCM] eisp_pc

Description: Xilinx Jtag Configuration source code, Support *.xsvf file-Xilinx Configuration source code, Support xsvf file*.
Platform: | Size: 1177600 | Author: lailing | Hits:

[Education soft system] PicoBlaze_03292006

Description: 基于Xilinx PicoBlaze处理器内核的系统 源代码-based Xilinx PicoBlaze processor system source code
Platform: | Size: 1616896 | Author: iorishen | Hits:

[VHDL-FPGA-Verilog] fixed_pointDivider

Description: 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
Platform: | Size: 397312 | Author: litao | Hits:

[VHDL-FPGA-Verilog] SS7160.ZIP

Description: 该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
Platform: | Size: 720896 | Author: 王珏 | Hits:
« 1 2 3 4 5 6 78 9 10 11 12 ... 50 »

CodeBus www.codebus.net