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[Other resource] watch2

Description: vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
Platform: | Size: 1071 | Author: rain | Hits:

[Other resource] WatchDog

Description: 对与单片机常用的功能看门狗，本程序用vhdl硬件语言实现次功能。
Platform: | Size: 1284 | Author: 姚大雷 | Hits:

[VHDL-FPGA-Verilog] watch_dog_rtl_source

Description: watch dog written in vhdl and has been imp.
Platform: | Size: 10271 | Author: bluemare | Hits:

[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[VHDL-FPGA-Verilog] watch2

Description: vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] watchdog.tar

Description: verilog编写的watchdog代码!请参考！-Verilog code watchdog prepared! please refer to!
Platform: | Size: 2048 | Author: 刘志刚 | Hits:

[VHDL-FPGA-Verilog] WatchDog

Description: 对与单片机常用的功能看门狗，本程序用vhdl硬件语言实现次功能。-Commonly used with single-chip watchdog function, the procedures for using VHDL hardware language functions realize times.
Platform: | Size: 1024 | Author: 姚大雷 | Hits:

[Software Engineering] watchver

Description: watchdog with verilog
Platform: | Size: 141312 | Author: Y.D. chang | Hits:

[VHDL-FPGA-Verilog] state_machine_watchdog

Description: 基于状态机的CPLD/FPGA看门狗程序 难能可贵-State machine based on the CPLD/FPGA valuable watchdog process
Platform: | Size: 650240 | Author: ld | Hits:

[VHDL-FPGA-Verilog] watch_dog_rtl_source

Description: Watchdog timer verilog RTL code
Platform: | Size: 10240 | Author: Chris | Hits:

[VHDL-FPGA-Verilog] VHDLbasicExampleDEVELOPEMENTsoursE

Description: 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用，介绍如下： Chapter3：schematic和vhdl文件夹，分别是数字钟设计的原理图文件和VHDL程序； Chapter4：multiplier文件夹，串并乘法器设计程序（提示：先编译程序包）； Chapter5：sci文件夹，串行通信接口设计程序； Chapter6：watchdog文件夹，看门狗设计程序； Chapter7：taxi文件夹，出租车计价器设计程序； Chapter8：elevator文件夹，高层电梯控制器设计程序； Chapter9：cymometer1和cymometer2文件夹，前者是计数测频设计程序，后者是等精度测频设计程序； Chapter10：digital_lock文件夹，数字密码锁设计程序； Chapter11：I2C文件夹，I2C控制器设计程序； Chapter12：fifo文件夹，异步FIFO设计程序； Chapter13：dds文件夹，数字频率合成设计程序； Chapter14：vLA文件夹，虚拟逻辑分析仪设计程序。 -this book includes 12 detail examples of the source program
Platform: | Size: 139264 | Author: wuyu | Hits:

[VHDL-FPGA-Verilog] watchdog

Description: 看门狗定时器Verilog源码；用于MCU的辅助模块，定时特定的时间来做硬件复位，是用于避免固件跑死的一个机制。-Watchdog verilog source.
Platform: | Size: 4096 | Author: 郑佛少 | Hits:

[OS program] Watchdog

Description: 基于ＶＨＤＬ语言，实用的看门狗功能设计程序-Based on the VHDL language, and practical watchdog function of the design process
Platform: | Size: 4096 | Author: 小涛 | Hits:

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