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[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[VHDL-FPGA-Verilog] watch2

Description: vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] watchdog.tar

Description: verilog编写的watchdog代码!请参考！-Verilog code watchdog prepared! please refer to!
Platform: | Size: 2048 | Author: 刘志刚 | Hits:

[Software Engineering] watchver

Description: watchdog with verilog
Platform: | Size: 141312 | Author: Y.D. chang | Hits:

[VHDL-FPGA-Verilog] watch_dog_rtl_source

Description: Watchdog timer verilog RTL code
Platform: | Size: 10240 | Author: Chris | Hits:

[VHDL-FPGA-Verilog] watchdog

Description: 看门狗定时器Verilog源码；用于MCU的辅助模块，定时特定的时间来做硬件复位，是用于避免固件跑死的一个机制。-Watchdog verilog source.
Platform: | Size: 4096 | Author: 郑佛少 | Hits:

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