Search - vhdl test bench

[VHDL-FPGA-Verilog] Sparc_leon_VHDL

Description: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Platform: | Size: 1873920 | Author: 韩红 | Hits:

[VHDL-FPGA-Verilog] ceshixiangliang

Description: vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples--- corresponding Adder test vector (test bench). Txt
Platform: | Size: 11264 | Author: 陈丽 | Hits:

[Books] VHDL_TESTBENCH

Description: 怎样用VHDL写TESTBENCH.rar VHDL仿真-how to use VHDL to write VHDL simulation TESTBENCH.rar
Platform: | Size: 9594880 | Author: 高 | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] spi2-testbench

Description: test bench for spi communication
Platform: | Size: 1024 | Author: Onur | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

[VHDL-FPGA-Verilog] multiplier_8_bit

Description: This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.
Platform: | Size: 3072 | Author: KC.Park | Hits:

[Other] testbench

Description: 怎样编写仿真功能的测试文件（test bench）-Learning materials, how to prepare testbench
Platform: | Size: 2608128 | Author: sophie | Hits:

[VHDL-FPGA-Verilog] edge_detection

Description: edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
Platform: | Size: 34816 | Author: yahyajan | Hits:

[Other] add4bit

Description: 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
Platform: | Size: 813056 | Author: 祁才君 | Hits:

[VHDL-FPGA-Verilog] fft_gen

Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: | Size: 6144 | Author: Jayesh | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: This zip file contains the verilog source code for square root calculation and its test bench
Platform: | Size: 2048 | Author: Jaganathan | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_VHDL

Description: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM VHDL的模型；simulation包含VHDL测试平台、modelsim工程文、设计库函数；source包含vhdl源文件；synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test bench, modelsim project text, design library function source contains the vhdl source file synthesis comprehensive document that contains the project.
Platform: | Size: 886784 | Author: 陈少华 | Hits:

[VHDL-FPGA-Verilog] Xilinxtestbenchwriting

Description: This book is all about test bench writing in verilog and VHDL.
Platform: | Size: 479232 | Author: Abhi | Hits:

[VHDL-FPGA-Verilog] ASIC_VHDL_FPGA_design_lectureNotes

Description: 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content include basics of vhdl, design process, UART design, RTL design, test and debug etc,etc VERY helpful to VHDL learners. A MUST SEE !
Platform: | Size: 10332160 | Author: zhou | Hits:

[VHDL-FPGA-Verilog] code

Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
Platform: | Size: 5120 | Author: syamprasad | Hits:

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