Search - vhdl sin

[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code
Platform: | Size: 2048 | Author: 王森 | Hits:

[VHDL-FPGA-Verilog] sin

Description: sin產生器，可以於VHDL產生sin之數值波形，進而輸出至dac做轉換-sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
Platform: | Size: 1084416 | Author: lin | Hits:

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3687424 | Author: hawd | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Platform: | Size: 2529280 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] SIN

Description: 使用VHDL语言和CPLD芯片生成39KHz的信号-The use of VHDL language and CPLD chip 39KHz signal generated
Platform: | Size: 219136 | Author: Beyond | Hits:

[VHDL-FPGA-Verilog] sin.tar

Description: 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:

[ELanguage] sin

Description: 正弦信号发生器源文件实现正弦信号发生器，非常有用，欢迎下载。-Sinusoidal signal generator source file achieve sinusoidal signal generator, very useful and welcome to download.
Platform: | Size: 1024 | Author: lee | Hits:

[VHDL-FPGA-Verilog] RomNCO

Description: 基于NCO的数字控制振荡器。带测试程序，输出12位的COS和SIN波形。-Based on the digital control oscillator NCO. With test procedures, the output 12 of the COS and the SIN waveform.
Platform: | Size: 29696 | Author: 咚咚 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 用VHDL编写的实现EDA实验中显示sin波形代码。简单易懂，应该对大家都有帮助-VHDL prepared with the realization of the experiment showed that EDA code sin waveform. Easy-to-read, should help to everyone
Platform: | Size: 1024 | Author: 林怡 | Hits:

[DSP program] sin_cos

Description: Sin & Cos generator (one from DSP steps)
Platform: | Size: 38912 | Author: jools | Hits:

[Software Engineering] calculator

Description: calculator, sin ,cos,multi, loga,-calculator, sin ,cos,multi, loga,...
Platform: | Size: 3163136 | Author: khanh | Hits:

[SCM] dds_synthesizer_latest.tar

Description: dds synthizer used to generate digital cos and sin
Platform: | Size: 519168 | Author: ahmed | Hits:

[VHDL-FPGA-Verilog] dds-sin-generator

Description: 正铉波发生器 dds 一共有8个vhdl文件组成。其中dds为头文件-dds
Platform: | Size: 7168 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

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[VHDL-FPGA-Verilog] 8bitsine

[VHDL-FPGA-Verilog] cordic

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] SIN

[VHDL-FPGA-Verilog] sin.tar

[ELanguage] sin

[VHDL-FPGA-Verilog] RomNCO

[VHDL-FPGA-Verilog] sin

[DSP program] sin_cos

[Software Engineering] calculator

[SCM] dds_synthesizer_latest.tar

[VHDL-FPGA-Verilog] dds-sin-generator

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] cordic1

[assembly language] sin

[VHDL-FPGA-Verilog] sin

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