Search - vhdl sequence detector

[VHDL-FPGA-Verilog] xljcq

Description: 用vhdl语言实现序列检测器的设计这是学习VHDL语言的经典例子-Using VHDL language sequence detector design VHDL language learning this is a classic example of
Platform: | Size: 3072 | Author: 郭海东 | Hits:

Description: 这是序列检测器。串行序列产生是指根据时钟和相应的控制信号，产生稳定的单bit输出信号；监测器指根据相应时钟输入的电平序列，监测该序列中是否存在预设的序列，无论从第几个输入开始，只要存在，总能监测到。监测到予以标示。-This is the sequence detector. Have a serial sequence is defined as the clock and the corresponding control signal, producing a stable single-bit output signal monitor means the corresponding clock input sequence level, monitoring the sequence of the existence of the default sequence, whether from the first few enter a start, as long as there is, always monitored. Monitoring to be marked.
Platform: | Size: 101376 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] chk

Description: 本程序实现了一个序列检测器。当一串待检测的串行数据进入检测器后，若此数在每一位的连续检测中都与预置的密码数相同，则输出“A”,否则仍然输出“B”。-This procedure implements a sequence detector. When a string of serial data to be tested after entering the detector, if the number in each successive detection with the same number of preset password, then output A , otherwise the output is still B .
Platform: | Size: 1024 | Author: liushenshen | Hits:

[VHDL-FPGA-Verilog] detect

Description: 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。-A sequence detector design. Procedure is not a problem, the key is to understand the thinking of state machine programming.
Platform: | Size: 1024 | Author: chengpan | Hits:

[VHDL-FPGA-Verilog] sequence_inspector

Description: 序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号，这在数字通信领域中有广泛的应用。当序列检测器连续收到一组二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到连续的检测中收到每一位都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。并附有测试程序-Sequence detector can be used to detect one or a binary code consisting of pulse sequence signal, which in the field of digital communications in a wide range of applications. When the sequence detector row received a group of binary code, if this group of codes and detectors in the same pre-set code, then output 1, otherwise output 0. As a result of this test lies in the receipt of the correct code must be continuous, which requires detector must be remembered that the previous code and correct the correct sequence, until the continuous detection and received every preset number of correspond to the same code. In the detection process, any one of unequal status will be returned to the initial detection of a fresh start. With test procedures
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilog] JIANCHE

Description: 本设计是一个序列检测器，能够检测11位长的系列信号，根据需要可适当扩展其序列长度-The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
Platform: | Size: 342016 | Author: liuxiaozhong | Hits:

[VHDL-FPGA-Verilog] seg_test

Description: 基于VHDL的序列检测器设计-VHDL-based sequence detector design
Platform: | Size: 156672 | Author: peter | Hits:

[Other] code

Description: 使用状态机设计一个5位序列检测器。从一串二进制码中检测出一个已预置的5位二进制码-The use of state machines to design a sequence detector 5. From a string of binary code to detect a preset binary code of 5
Platform: | Size: 48128 | Author: evelyn | Hits:

[VHDL-FPGA-Verilog] 2

Description: 序列检测器VHDL语言设计和仿真和校验模块的程序和仿真结果 -Sequence detector design and simulation of VHDL language and the validation process modules and simulation results
Platform: | Size: 38912 | Author: 林露吟 | Hits:

[ELanguage] EP1C3_81_SCHK

Description: 序列检测器设计这里面是一个完整的工程可以直接适用-Sequence detector design there is a complete project can be applied directly
Platform: | Size: 7168 | Author: 小欧 | Hits:

[Windows Develop] Sequencedetector

Description: 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the pulse sequence signal, which is a broad field of digital communication applications. When the detector continuously received after a group of serial binary code, if this group of pre-code and the code detector in the same output as A, otherwise the output B. Sequence detection I/O port design are as follows: Let Din is the serial data input, clk is work the clock, clr is a reset signal, D is the 8-bit preset number to be detected, QQ is the test results output.
Platform: | Size: 4096 | Author: yufang | Hits:

[VHDL-FPGA-Verilog] fsm

Description: Sequence detector "1100101101" using FSM(Finite State Machine) in VHDL.
Platform: | Size: 401408 | Author: Aaqib | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 序列检测器设计VHDL源程序任意输入串行数据串-VHDL source code sequence detector design arbitrary string of serial data input
Platform: | Size: 1024 | Author: terry | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 检测一组或多组又二进制码组成的脉冲序列信号，当序列检测器连续收到一组或多组序列信号，如果与预先设置的码相同的时候，输出1，否则输出0. -Detection of one or more group was composed of binary code pulse train signal, when the sequence detector continuous sequence of one or more groups received signal, if the same code with pre-set time, output 1, otherwise output 0.
Platform: | Size: 124928 | Author: venny | Hits:

[VHDL-FPGA-Verilog] serial_check

Description: 本实验需要实现一个序列检测器，用来检测输入的串行位流是否和程序设定的位串相一致，若一致则在验证波形的出现一个高电位来表示。本实验需要验证的位串是“101011”。-In this study, need to implement a sequence detector, to detect whether the input serial bit stream and procedures consistent set of bit strings, if the same occurs in the verification of the waveform to represent a high potential. In this study, need to verify the bit string is " 101011."
Platform: | Size: 50176 | Author: 张洁 | Hits:

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