Location:
Search - vhdl matlab bit
Search list
Description: 8 位移位寄存器
VHDL程序 VHDL程序 VHDL程序-8-bit shift register VHDL procedures VHDL procedures VHDL procedures
Platform: |
Size: 197632 |
Author: 周辉 |
Hits:
Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: |
Size: 3072 |
Author: chenyi |
Hits:
Description: HART协议的均衡器设计 DCT LMS 设计 + 位同步设计，仿真证明了设计的有效性-HART protocol design DCT LMS equalizer design+ Bit synchronous design, simulation proves the validity of the design
Platform: |
Size: 21504 |
Author: 进正化 |
Hits:
Description: 本文提出了加快发展之路
从理论设计,通过Matlab / Simulink环境
在定点算法对其行为模拟的
在FPGA或定制实现硅片。这个了
实现了netlist移植的Simulink系统
描述成的硬件描述语言[VHDL]。在这个例子中,这个
Simulink-to-VHDL转换器被设计来使用
代码来描述结构VHDL系统互连,
允许简单的行为说明基本模块。
结果VHDL bit-true交付后代码
比较定点Simulink仿真模型等效
模拟。-This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.
Platform: |
Size: 147456 |
Author: 王晓 |
Hits:
Description: LDPC码既低密度奇偶校验码（Low Density Parity Check Code，LDPC），它由Robert G.Gallager博士于1963年提出的一类具有稀疏校验矩阵的线性分组码，不仅有逼近Shannon限的良好性能，而且译码复杂度较低, 结构灵活，是近年信道编码领域的研究热点，目前已广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域。LDPC码已成为第四代通信系统(4G)
-LDPC codes BER simulation under AWGN channel. MacKay-Neal based LDPC matrix. Message encoding uses sparse LU decomposition. There are 4 choices of decoder: hard-decision/bit-flip decoder, probability-domain SPA decoder, log-domain SPA decoder, and simplified log-domain SPA decoder.
Platform: |
Size: 8192 |
Author: 天天 |
Hits:
Description: 16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!
Platform: |
Size: 16425984 |
Author: 殷桃 |
Hits:
Description: 本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础
上，采用超高速集成电路硬件描述语言(VeryHighspeedxntegatedeireuitHardware
DescriptionLan即age，简称VHDL)在Altera公司 Quartusll7.0开发环境下设计并实现各个功能块，通过仿真来证明功能正确性。再次，用 Protel99SE进行印制电路板(Prinicircuitboard，简称PcB)设计，从原理图到封装，再到布局布线。焊接调试完毕后，将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbPs，调制中频10MHz。测试结果验证系统的正确性，实现了从数字基带到中频的可4一DQPSK调制解调系统-This study is the first 4 1 DQPsK modem modulation system, part of the basic principles and design of each module, focusing on shaping filter and a direct digital frequency synthesizer (DireetoigitalFrequeneySynihesis, referred to as DDS), and to address all the key modules algorithm matlab design simulation to show simulation results. Second, the study of modulation and demodulation system demodulation part of the basic principles and design of each module, focusing on differential demodulation, digital down conversion and bit synchronization algorithm, but also for its various key module of the Matlab algorithm design and simulation. Then use the Matlab simulation of the entire system theory, reach a conclusion. On this basis,
, Using ultra-high speed integrated circuit hardware description language (VeryHighspeedxntegatedeireuitHardware
DescriptionLan that age, referred to as VHDL) in the Altera Corporation Quartusll7.0 development environment to design and implement the variou
Platform: |
Size: 5457920 |
Author: cai |
Hits:
Description: This paper presents the way of speeding up the route
from the oretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.-This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.
Platform: |
Size: 147456 |
Author: jack |
Hits:
Description: 用2个2级iir滤波实现的4阶iir滤波，采用16bit量化系数，其中14位有效位，经过与matlab的4阶iir滤波对比，输出结果完全一致。(The 4 order IIR filtering is implemented by two 2-level IIR filtering, and the 16bit quantization coefficient is adopted, in which 14 bit effective bits are compared with the 4 order IIR filtering of MATLAB, and the output results are exactly the same.)
Platform: |
Size: 1024 |
Author: 马克西姆023
|
Hits:
Description: 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specified MAC - based bandpass filter using the basic block of the system generator)
Platform: |
Size: 800768 |
Author: 瑞雪儿
|
Hits: