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[VHDL-FPGA-Verilog] DIGTAL_FIR

Description: 环路滤波器的设计，基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Platform: | Size: 774144 | Author: 梁大法 | Hits:

[Other] ChargePumpPLL

Description: An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL.pdf This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase- Frequency Detector and a current switch charge pump.-An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL.pdf This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase-Frequency Detector and a current switch charge pump.
Platform: | Size: 129024 | Author: 刘洋 | Hits:

[VHDL-FPGA-Verilog] PN_code_capture_and_tracing

Description: 一个完整的pn码捕获与跟踪的VHDL源码,并行匹配滤波器捕获,锁相环跟踪.-A complete pn Code Acquisition and Tracking of the VHDL source code, parallel matched filter to capture, phase-locked loop tracking.
Platform: | Size: 2048 | Author: 王永俊 | Hits:

[VHDL-FPGA-Verilog] code

Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
Platform: | Size: 5120 | Author: syamprasad | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] costas

Description: costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Platform: | Size: 6144 | Author: 潇潇 | Hits:

[VHDL-FPGA-Verilog] FIR-LOOP-

Description: 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
Platform: | Size: 1024 | Author: rickdecent | Hits:

[Communication] LoopFilter

Description: 科斯塔斯环环路滤波器的VHDL实现，仅工参考-VHDL Implementation of Costas Loop the loop filter, the only work of reference
Platform: | Size: 1024 | Author: sheweidong | Hits:

[Communication] (costas)max_choice

Description: 科斯塔斯环环路滤波器的VHDL实现，仅供参考-VHDL Implementation of Costas Loop the loop filter, the only work of reference
Platform: | Size: 3072 | Author: sheweidong | Hits:

[transportation applications] LoopFilter

Description: 这是锁相环的环路滤波器实现。其中采用的是串行的实现结构-This is the PLL loop filter VHDL implementation. Using a serial implementation structure
Platform: | Size: 1024 | Author: LUOLIUZSHEN | Hits:

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