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[VHDL-FPGA-Verilog] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Platform: | Size: 8431616 | Author: 杨奋燕 | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。 因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[SCM] 7

Description: 单片机源码，实现按键时间计时兵得出平均时间。富电路图和源码-Single-chip source, time to achieve key time soldiers come to the average amount of time. Fu schematics and source code
Platform: | Size: 59392 | Author: luoyouhao | Hits:

[VHDL-FPGA-Verilog] fpga

Description: 无线光通信技术具有通信容量大、传输速率高等众多优点, 在许多场合都有重要的应用, 是现代通信技术研究的一个热点。由于脉冲位置调制 ( PPM ) 有较高的平均功率利用率和抗干扰能力, 故 PPM是无线光通信系统中常用的调制方式。在研究 PPM调制技术的基础上, 就基于 FPG A的无线光通信 PPM调制系统进行设计, 并用 V H D L语言完成了系统的设计和仿真。仿真结果表明, 该设计具有正确性和合理性。-Wireless optical communication technology has the communications capacity, many of the benefits of higher transmission rates, in many occasions have important applications in modern communication technologies are a hot research. Because of pulse position modulation (PPM) have a higher average power utilization and anti-interference ability, so PPM is a wireless optical communication system commonly used in modulation. PPM modulation technique in the study on the basis of FPG A based on wireless optical communication PPM modulation system design, and VHDL language achieve the system design and simulation. Simulation results show that the rationality of the design right.
Platform: | Size: 194560 | Author: 朱雯 | Hits:

[VHDL-FPGA-Verilog] MediaMobile

Description: moving average vhdl source code
Platform: | Size: 1024 | Author: gnomix | Hits:

[VHDL-FPGA-Verilog] MovingAverageFilter

Description: This zip file contains the moving average filter code written in verilog HDL
Platform: | Size: 1147904 | Author: Jagan | Hits:

[VHDL-FPGA-Verilog] Moving_average_algorithm

Description: Document detailing the moving average algorithm.
Platform: | Size: 60416 | Author: mcholbi | Hits:

[VHDL-FPGA-Verilog] mean

Description: 3x3 Average filter in VHDL
Platform: | Size: 1024 | Author: Gimutsh | Hits:

[VHDL-FPGA-Verilog] mov-avg

Description: moving average VHDl implementation
Platform: | Size: 27648 | Author: dev | Hits:

[VHDL-FPGA-Verilog] 2012-05-27-ADC-Light-Sensor-Avago-APDS-9005-020.z

Description: ADC Light Sensor Avago APDS-9005-020 VHDL solution running on a Xilinx Spartan 6: Reading out light intensity from an Avago APDS-9005-020 using an average DAC and two additional digital control lines.
Platform: | Size: 1354752 | Author: Abel Tazzman | Hits:

[VHDL-FPGA-Verilog] Extra-Excercise---Moving-Average-Jiten-Bhatt-1130

Description: VHDL code on implementing a system to calculate moving average
Platform: | Size: 151552 | Author: Parvathy | Hits:

[VHDL-FPGA-Verilog] AVER

Description: 用vhdl实现数值的平均，用quartus||实现编译下载-Using vhdl average values, with quartus | | realized compiled download
Platform: | Size: 239616 | Author: kempwangkai | Hits:

[Software Engineering] dianzimimashuolunwen

Description: 为了使现在的电子密码锁更能智能化的管理，让人们更能方便的使用，让其具有更高的安全性和经济性，针对基于单片机的电子密码锁的不足之处，本文采用EDA技术，利用QuartusⅡ工作平台硬件描述语言，设计一种电子密码锁，并通过一片FPGA芯片实现。采用VHDL语言使用自顶向下的方法对系统进行了描述，并在FPGA芯片CycloneⅡ上实现。设计充分利用了FPGA的资源可编程特性，可高效率的对系统进行升级与改进。设计的密码锁可设置任意密码，比一般的四位密码锁具有更高的安全可靠性，因此，采用FPGA 开发的数字系统,不仅具有很高的工作可靠性,其升级与改进也极其方便，应用前景十分良好。-In order to make electronic locks now more intelligent management, so that people more convenient to use, let it have a higher level of security and economy, the inadequacy of microcontroller based electronic locks for, we use EDA technology by QuartusⅡ work platform hardware description language design an electronic lock, and through an FPGA chip. Methods of VHDL using a top-down system are described and implemented in the FPGA chip CycloneⅡ. Designed to take full advantage of the resources of FPGA programmable features, high efficiency of the system can be upgraded and improved. Design can set any password lock, password lock than the average of four has higher safety and reliability, therefore, the use of FPGA development of digital systems, not only has high reliability, it is also extremely easy to upgrade and improvement, prospects are very good.
Platform: | Size: 542720 | Author: 许家硕 | Hits:

[VHDL-FPGA-Verilog] w1

Description: 基于VHDL语言编写的EDA程序，可试验大月小月，润年平年的自行进位，也可手动调时。-Based on EDA VHDL language program, you can test large Satsuki month, leap year self-carry average year, you can manually adjust the time.
Platform: | Size: 2242560 | Author: 齐天力 | Hits:

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