Search - vhdl 3-8 decoder

[assembly language] VHDL3-8

Description: 用VHDL设计的3-8译码器，精简~！-design using VHDL 3-8 decoder, streamlining ~!
Platform: | Size: 2538 | Author: sfdfsdf | Hits:

[Other resource] 3-8译码器

Description: vhdl的3-8译码器-instantiate the 3-8 decoder
Platform: | Size: 999504 | Author: 熊辉波 | Hits:

[VHDL-FPGA-Verilog] 3-8译码器

Description: vhdl的3-8译码器-instantiate the 3-8 decoder
Platform: | Size: 999424 | Author: 熊辉波 | Hits:

[assembly language] VHDL3-8

Description: 用VHDL设计的3-8译码器，精简~！-design using VHDL 3-8 decoder, streamlining ~!
Platform: | Size: 2048 | Author: sfdfsdf | Hits:

[Embeded-SCM Develop] 3-8TRANSFORMER

Description: 译码器的逻辑功能是将已赋予特定含义的一组二进制输入代码的原意"翻译"出来,变成对应的输出高低电平信号.该程序为3-8译码器.基于VHDL,其开发环境是MAXPLUS2.-Decoder logic function is to have been given the specific meaning of a group of binary code input the original intent of translation out into the corresponding output high-low-level signals. The program for the 3-8 decoder. Based on VHDL, its development The environment is MAXPLUS2.
Platform: | Size: 4096 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] 3-8

Description: 本文件是利用verilog实现的3-8译码器-This document is the use of Verilog realize the 3-8 decoder
Platform: | Size: 2048 | Author: 阿岩 | Hits:

[VHDL-FPGA-Verilog] MyProject

Description: 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3，原理图源文件保存在MyProject目录中，为138decoder.gdf，另有我写的实验报告，呵呵，适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyProject directory for 138decoder.gdf, otherwise I write experimental reports, Ha ha, suitable for simulation of induction
Platform: | Size: 224256 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] 3_8_decoder

Description: 利用CASE语句的3-8译码器,3个为数据输入,3个为控制端,分别为S1,S2,S3,输出数据为八位-Use CASE statement 3-8 decoder, three for data entry, three for the control side, namely S1, S2, S3, output data for eight
Platform: | Size: 131072 | Author: sunrier | Hits:

[VHDL-FPGA-Verilog] chap9

Description: 用assign 语句描述的三态门，三态双向驱动器，3-8 译码器，8-3 优先编码器-With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
Platform: | Size: 7168 | Author: chencong | Hits:

[VHDL-FPGA-Verilog] encoderdecoder

Description: this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 142336 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。 -EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.
Platform: | Size: 797696 | Author: pear | Hits:

[VHDL-FPGA-Verilog] 3-8xianyimaqi

Description: VHDL语言实现3-8线译码器，带仿真波形图，和管脚分布图-VHDLLanguage 3-8 line decoder
Platform: | Size: 30720 | Author: 该改 | Hits:

[VHDL-FPGA-Verilog] 3-8decoder

Description: FPGA/CPLD的开发，基于VHDL语言编写的3-8译码器，供大家参考-Based on the VHDL language 3-8 decoder
Platform: | Size: 234496 | Author: 刘志芳 | Hits:

[VHDL-FPGA-Verilog] 3_8-decoder

Description: CPLD EPM1270 VHDL 3-8译码器。-CPLD EPM1270 VHDL 3-8 decoder.
Platform: | Size: 188416 | Author: 丹丹 | Hits:

[Other] vhdl

Description: 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
Platform: | Size: 1024 | Author: lailai | Hits:

[assembly language] vhdl

Description: 译码器设计实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and downloaded to the development board for verification. Using DIP switch block K1, K2, K3 of the three binary code as input, output 8 yards respectively show LED1 ~ LED8
Platform: | Size: 265216 | Author: 阮智钦 | Hits:

[VHDL-FPGA-Verilog] 3-8yimaqi

Description: 详细介绍了VHDL中3-8译码器，适合初学者-Details of the 3-8 decoder VHDL, suitable for beginners
Platform: | Size: 911360 | Author: 王先生 | Hits:

[VHDL-FPGA-Verilog] 1

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc..)
Platform: | Size: 453632 | Author: zidting | Hits:

[Communication-Mobile] ENCODER38

Description: 基于fpga的vhdl的3-8译码器程序。可以有效译码(3 8 decoder base on vhdl.)
Platform: | Size: 293888 | Author: Mr.zeal | Hits:

[VHDL-FPGA-Verilog] 3-8译码器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination of the 3-8 decoder logic device)
Platform: | Size: 10240 | Author: lixilin | Hits:

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[assembly language] VHDL3-8

[Other resource] 3-8译码器

[VHDL-FPGA-Verilog] 3-8译码器

[assembly language] VHDL3-8

[Embeded-SCM Develop] 3-8TRANSFORMER

[VHDL-FPGA-Verilog] 3-8

[VHDL-FPGA-Verilog] MyProject

[VHDL-FPGA-Verilog] 3_8_decoder

[VHDL-FPGA-Verilog] chap9

[VHDL-FPGA-Verilog] encoderdecoder

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] 3-8xianyimaqi

[VHDL-FPGA-Verilog] 3-8decoder

[VHDL-FPGA-Verilog] 3_8-decoder

[Other] vhdl

[assembly language] vhdl

[VHDL-FPGA-Verilog] 3-8yimaqi

[VHDL-FPGA-Verilog] 1

[Communication-Mobile] ENCODER38

[VHDL-FPGA-Verilog] 3-8译码器VHDL描述

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