Search - verilog epm240

[VHDL-FPGA-Verilog] lcdexample

Description: cpld实现与液晶屏并口通信，VHDL 语言编程。对VHDL初学者应该有帮助的。-cpld achieve parallel with the LCD screen communications, VHDL programming. Right VHDL beginners should help.
Platform: | Size: 1024 | Author: 黄小光 | Hits:

[VHDL-FPGA-Verilog] EPM240Prj

Description: 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.-This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plus 1 per second. Quartus ii 7.0 use more than open.
Platform: | Size: 521216 | Author: 白蚁 | Hits:

[VHDL-FPGA-Verilog] SRAM_read_and_write

Description:
Platform: | Size: 462848 | Author: 王建毅 | Hits:

[VHDL-FPGA-Verilog] EPM240_SCH_and_program

Description: EPM240 cpld 原理图+程序。 Verilog HDL语言。程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。-Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display program, counters and so on.
Platform: | Size: 660480 | Author: student88 | Hits:

[ARM-PowerPC-ColdFire-MIPS] vgactl9

Description: EPM240+IS61LV1024+VERILOG实现简单的VGA控制器,RGB各1bit,与AT91SAM7S64接口.-EPM240+ IS61LV1024+ VERILOG to achieve a simple VGA controller, RGB each 1bit, and AT91SAM7S64 interface.
Platform: | Size: 563200 | Author: 刘聪 | Hits:

[VHDL-FPGA-Verilog] armledctl

Description: EPM240+IS61LV1024+VERILOG实现LED显示控制,1红+1绿,1280*512,与AT91SAM7S64接口-EPM240+ IS61LV1024+ VERILOG to achieve LED display control, 1 red+ 1 green, and 1280* 512, and AT91SAM7S64 Interface
Platform: | Size: 566272 | Author: 刘聪 | Hits:

[VHDL-FPGA-Verilog] VGA_test50m

Description: 本代码功能为实现VGA显示功能，即实现在显示器上显示640*480彩条。程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve the VGA display, that is, to achieve the display 640* 480 Color display. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 47104 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] IR

Description: 本代码功能为实现38/30KHZ红外线接收功能程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve 38/30KHZ infrared reception procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 78848 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] ps2test

Description: 本代码功能为实现接收PS2键盘编码功能。程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve the receiver PS2 keyboard encoding. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 118784 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] recuart_50m

Description: 本代码功能为实现接收PC发送的串口数据功能程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve the receiving PC to send serial data capabilities procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 48128 | Author: huangbin | Hits:

[VHDL-FPGA-Verilog] halfclk

Description: 本代码功能为实现输入时钟的1.5分频功能。程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions as the input clock frequency of 1.5 features. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 28672 | Author: huangbin | Hits:

[VHDL-FPGA-Verilog] EPM240_analog_lcd_moudle_controller(sch_pcb_democo

Description: EPM240做的模拟屏控制器，有原理图（PDF）,PCB(PDF),手册（DOC）,程序（verilog），PIN文件。淘宝上有得买-EPM240 analog LCD moudle controller with schematic，PCB,demo code，handbook，pin assiment file。
Platform: | Size: 497664 | Author: SEED | Hits:

[VHDL-FPGA-Verilog] EPM240_Uart

Description: 基于Quartus II的Verilog编写的Uart串口测试程序。数据收发机LED灯测试。-Based on the Verilog Quartus II prepared Uart serial port test program. LED lamp test data transceiver.
Platform: | Size: 258048 | Author: | Hits:

[VHDL-FPGA-Verilog] clkdivverilog

Description: Verilog的时钟分频程序基于EPM240的入门实验特权同学-Verilog program the clock frequency of entry based on experimental privileged students EPM240
Platform: | Size: 159744 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] EPM240

Description: 开发板配套教程里的很多个实验方便从初学开始含有VHDL和verilog HDL语言-Development board supporting the many tutorial easy experiments start from the beginner with the language VHDL and verilog HDL
Platform: | Size: 14445568 | Author: menshen08 | Hits:

[VHDL-FPGA-Verilog] EPM240-board

Description: 基于EPM240的入门实验拥有大量的实验历程完全可以学习掌握Verilog语言。-Based on the the EPM240 entry experiments have a large number of experimental course can learn to master the Verilog language.
Platform: | Size: 1527808 | Author: gcy | Hits:

[VHDL-FPGA-Verilog] EPM240

Description: 深入浅出玩转FPGA一书的基础实验源代码，采用Verilog描述-FPGA source code
Platform: | Size: 2770944 | Author: wjc | Hits:

[VHDL-FPGA-Verilog] EPM240例程

Description: 很好用的VERILOG代码程序，大家可以下载使用(Very good VERILOG code procedures, we can download to use)
Platform: | Size: 3452928 | Author: 刘龘赟 | Hits:

[Embeded-SCM Develop] Lesson07：BJ-EPM240学习板实验1——分频计数实验

Description: Quartus的分频计数试验视频讲解,讲解的很详细，对于新手来说还是蛮不错的(Quartus_frequency division technology test video explanation)
Platform: | Size: 79254528 | Author: YouKnowWho | Hits:

[VHDL-FPGA-Verilog] Lesson09：BJ-EPM240学习板实验2——按键消抖实验

Description: Quartus的按键消抖设计实验视频讲解,讲解的很详细，对于新手来说还是蛮不错的(Quartus key to shake down the design of experimental video explanation)
Platform: | Size: 46035968 | Author: YouKnowWho | Hits:

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[VHDL-FPGA-Verilog] lcdexample

[VHDL-FPGA-Verilog] EPM240Prj

[VHDL-FPGA-Verilog] SRAM_read_and_write

[VHDL-FPGA-Verilog] EPM240_SCH_and_program

[ARM-PowerPC-ColdFire-MIPS] vgactl9

[VHDL-FPGA-Verilog] armledctl

[VHDL-FPGA-Verilog] VGA_test50m

[VHDL-FPGA-Verilog] IR

[VHDL-FPGA-Verilog] ps2test

[VHDL-FPGA-Verilog] recuart_50m

[VHDL-FPGA-Verilog] halfclk

[VHDL-FPGA-Verilog] EPM240_analog_lcd_moudle_controller(sch_pcb_democo

[VHDL-FPGA-Verilog] EPM240_Uart

[VHDL-FPGA-Verilog] clkdivverilog

[VHDL-FPGA-Verilog] EPM240

[VHDL-FPGA-Verilog] EPM240-board

[VHDL-FPGA-Verilog] EPM240

[VHDL-FPGA-Verilog] EPM240例程

[Embeded-SCM Develop] Lesson07：BJ-EPM240学习板实验1——分频计数实验

[VHDL-FPGA-Verilog] Lesson09：BJ-EPM240学习板实验2——按键消抖实验

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