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[VHDL-FPGA-Verilog] VHDL实例

Description: 各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format
Platform: | Size: 168960 | Author: 付杰 | Hits:

[VHDL-FPGA-Verilog] 8位大小比较器

Description: 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
Platform: | Size: 1024 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] Sobel--Image_Filter_An_Image_filtering_VHDL

Description: Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip-Sobel-- Image Filter (I). An Image filteri Vi is made over the data loaded into RAM on board a nd presented on a VGA monitor.zip
Platform: | Size: 316416 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] maxbijiao

Description: 在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory
Platform: | Size: 30720 | Author: 王金栓 | Hits:

[VHDL-FPGA-Verilog] 8bit_cample

Description: 这是用数据流来设计的8位比较器,很简单,也很使用,希望能有所帮助,谢谢批评指导-This is used to design data stream 8-bit comparators, is simple and the use of, hoping to be helpful, thank you criticize guidance
Platform: | Size: 2048 | Author: 赵正鑫 | Hits:

[ActiveX/DCOM/ATL] comparator

Description: 一个verilog源代码，作用是比较器的实验程序。-A verilog source code, the role of the experimental procedures comparator.
Platform: | Size: 67584 | Author: PUDN_CHEN | Hits:

[VHDL-FPGA-Verilog] compare8

Description: 一个用Verilog语言实现的八位二进制数比较器。包含工程文件和实现文档。-One with the Verilog language implementation of the eight binary comparator. And the achievement of the document contains the project file.
Platform: | Size: 102400 | Author: 文闯 | Hits:

[VHDL-FPGA-Verilog] comp

Description: 数值比较器，Verilog实现，带具体实验说明文档。-Numerical comparator, Verilog realization of experiments with specific documentation.
Platform: | Size: 755712 | Author: mypudn0001 | Hits:

[VHDL-FPGA-Verilog] chengxu

Description: 加法器 比较器verilog hdl 等简单小程序 新手学习中 见谅-Adder comparator verilog hdl Adder comparator verilog hdl a small way as simple novice learning apologize
Platform: | Size: 1024 | Author: 张俊 | Hits:

[VHDL-FPGA-Verilog] compare

Description: 一个用verilog写的基本的比较器，其中带了一些其他的电路，也是用verilog编的，希望对读者有用。-Use verilog to write a basic comparator, which brought a number of other circuits, but also with the verilog code, and I hope useful to readers.
Platform: | Size: 125952 | Author: lixu | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 一些用verilog编写的小程序，有全加器，计数器，比较器VGA显示，键盘扫描等-Some small programs written using verilog have full adder, counter, comparator VGA display, keyboard scanning, etc.
Platform: | Size: 8904704 | Author: 于苏 | Hits:

[VHDL-FPGA-Verilog] comparator

Description: 8位二进制的数值比较器，这是用verilog hdl语言中的行为建模写的-8-bit binary value of the comparator, which is used in the verilog hdl behavioral modeling language to write
Platform: | Size: 147456 | Author: 黄启 | Hits:

[VHDL-FPGA-Verilog] comparator

Description: 使用verilog语言，在FPGA开发工具ISE上实现比较器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the comparator function.
Platform: | Size: 629760 | Author: 丁帅 | Hits:

[Other] magnitude-comparator-and-mux

Description: Magnitude comparator and multiplexer codes in Verilog
Platform: | Size: 1024 | Author: pravat | Hits:

[VHDL-FPGA-Verilog] verilog-code-FOR-COMPARATOR--TFF-AND-BCD-TO-7SSD.

Description: // File : 4 Bit Comparator design using behavior modeling style.v-// File : 4 Bit Comparator design using behavior modeling style.v
Platform: | Size: 2048 | Author: dhishna | Hits:

[Software Engineering] mixed-language--desvription-of-a-4x4-comparator.z

Description: mixed language (i.e VHDL and verilog ) is used to compute 4x4 comparator.. vhdl full adder is imported to verilog main module.
Platform: | Size: 1024 | Author: naz | Hits:

[VHDL-FPGA-Verilog] Comparator

Description: Verilog program for an 8bit up down counter
Platform: | Size: 465920 | Author: tom | Hits:

[VHDL-FPGA-Verilog] comparator

Description: COMPERATOR 2位比较器，含测试(COMPERATOR 2 bit comparator, including testbanch)
Platform: | Size: 1024 | Author: sunyp24 | Hits:

[ARM-PowerPC-ColdFire-MIPS] vivado

Description: 用中规模MSI基本逻辑功能模块 实现关模比较器（要求分别使用中规模和语言实现）： 功能要求：它的输入是两个8位无符号二进制整数X和Y，以及一个控制信号S；输出信号为1个8位无符号二进制整数Z。输入输出关系为：当S=1时， Z=min(X,Y)；当S=0时， Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale and language are required respectively): Functional requirements: Its input is two 8-bit unsigned binary integers X and Y, and a control signal S; the output signal is an 8-bit unsigned binary integer Z. The relationship between input and output is: when S = 1, Z = min (X, Y); when S = 0, Z = max (X, Y).)
Platform: | Size: 10240 | Author: 瘾1581 | Hits:

[VHDL-FPGA-Verilog] test1

Description: 该程序实现的是一个比较器，输入两个数字，进行比较，将结果输出(The program implements a comparator that inputs two numbers, compares them, and outputs the results.)
Platform: | Size: 33792 | Author: hello_tr | Hits:
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