Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: comp Download
 Description: Numerical comparator, Verilog realization of experiments with specific documentation.
 Downloaders recently: [More information of uploader mypudn0001]
  • [Verilog-statemachine] - use Verilog Programming state machine ex
  • [VERILOGCOMP] - design a byte (8) for comparison. Requir
  • [FIFO] - Asynchronous FIFO verilog realize realiz
  • [compare_4] - 4 comparator, through the VHDL language
  • [comparison] - 4-bit binary comparator, compare two bin
  • [verilog] - Verilog language used to describe compar
  • [xulijieceqi] - xuliejieceqi
  • [verilog] - verilog programming in the basic procedu
  • [compare] - Comparators implemented Verilog, contain
  • [comparator] - 8-bit binary value of the comparator, wh
File list (Check if you may need any files):
数值比较器实验例程及文档
........................\comp
........................\....\comp.prj
........................\....\component
........................\....\constraint
........................\....\coreconsole
........................\....\designer
........................\....\........\impl1
........................\....\........\.....\comp.adb
........................\....\........\.....\comp.dtf
........................\....\........\.....\........\verify.log
........................\....\........\.....\comp.ide_des
........................\....\........\.....\comp.pdb
........................\....\........\.....\comp.pdb.depends
........................\....\........\.....\comp.tcl
........................\....\........\.....\comp_fp
........................\....\........\.....\.......\$$FlashPro_FPBBALTLPT1.L$$
........................\....\........\.....\.......\comp.log
........................\....\........\.....\.......\comp.pro
........................\....\........\.....\.......\projectData
........................\....\........\.....\.......\...........\comp.pdb
........................\....\........\.....\designer.log
........................\....\........\.....\simulation
........................\....\hdl
........................\....\...\comp.v
........................\....\phy_synthesis
........................\....\simulation
........................\....\..........\modelsim.ini
........................\....\smartgen
........................\....\........\smartgen.aws
........................\....\stimulus
........................\....\synthesis
........................\....\.........\.recordref
........................\....\.........\backup
........................\....\.........\comp.areasrr
........................\....\.........\comp.edn
........................\....\.........\comp.map
........................\....\.........\comp.pdc
........................\....\.........\comp.sdf
........................\....\.........\comp.so
........................\....\.........\comp.srd
........................\....\.........\comp.srm
........................\....\.........\comp.srr
........................\....\.........\comp.srs
........................\....\.........\comp.szr
........................\....\.........\comp.tlg
........................\....\.........\comp_sdc.sdc
........................\....\.........\comp_syn.prj
........................\....\.........\coreip
........................\....\.........\run_options.txt
........................\....\.........\stdout.log
........................\....\.........\syntmp
........................\....\.........\......\comp.plg
........................\....\.........\traplog.tlg
........................\....\viewdraw
........................\....\........\sch
........................\....\........\sym
........................\....\........\vf
........................\....\........\..\project.lst
........................\....\........\viewdraw.ini
........................\....\........\wir
........................\数值比较器.pdf
    

CodeBus www.codebus.net