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[Other Embeded program] uart_rx

Description: actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码-actel A3P250 fpga with VERILOG HDL Serial functional language source code
Platform: | Size: 533504 | Author: wuqj | Hits:

[VHDL-FPGA-Verilog] UART_send

Description: Verilog HDL 串口发送程序，在ACTEL Fusion FPGA上实验成功 ，和大家一起分享！^_^-Verilog HDL send serial procedures, ACTEL Fusion FPGA in the success of the experiment, and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[VHDL-FPGA-Verilog] UART_rec

Description: verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功 和大家一起分享！^_^-Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[Other Embeded program] UART

Description: 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5-The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
Platform: | Size: 285696 | Author: grqd | Hits:

[VHDL-FPGA-Verilog] my_and

Description: 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.
Platform: | Size: 902144 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] Libra_ps2key_lcd

Description: 用Verilog语言实现的PS2小键盘输入和1602 LCD显示的功能。无需修改，已经调试通过了。直接可以当成一个模块用于FPGA/CPLD系统开发过程。 这个代码是我在Libra环境下开发Actel FPGA时写的。-Verilog language using the PS2 keyboard and a small 1602 LCD display features. No changes have been adopted debugging. Directly as a module for the FPGA/CPLD system development process. This code is my development environment in Libra when written in Actel FPGA.
Platform: | Size: 6144 | Author: 赵二虎 | Hits:

[VHDL-FPGA-Verilog] hdlcode_ug

Description: Verilog HDL Coding Guidelines - ACTEL -Verilog HDL Coding Guidelines- ACTEL
Platform: | Size: 2143232 | Author: Chetan | Hits:

[VHDL-FPGA-Verilog] hdl

Description: ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
Platform: | Size: 3072 | Author: gouyouwen | Hits:

[VHDL-FPGA-Verilog] hdl

Description: ACTEL FPGA 1602显示，verilog描述-ACTEL FPGA 1602 show, verilog description
Platform: | Size: 3072 | Author: gouyouwen | Hits:

[VHDL-FPGA-Verilog] hdl

Description: ACTEL FPGA 交通灯，Verilog描述-ACTEL FPGA traffic lights, Verilog description
Platform: | Size: 6144 | Author: gouyouwen | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码-actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL
Platform: | Size: 608256 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] RTC

Description: actel fpga开发板fusion startkit实验例程，包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
Platform: | Size: 2233344 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] D_latch

Description: actel fpga Verilog D锁存器-actel fpga Verilog D latch
Platform: | Size: 130048 | Author: zhongpeng | Hits:

[VHDL-FPGA-Verilog] my_RAM

Description: pdf actel fpga verilog ram读写-pdf actel fpga verilog ram read and write
Platform: | Size: 2410496 | Author: zhongpeng | Hits:

[VHDL-FPGA-Verilog] AES_test

Description: verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
Platform: | Size: 112640 | Author: zhongpeng | Hits:

[VHDL-FPGA-Verilog] FlashLock_test

Description: pdf actel fpga verilog FLASH读写-pdf actel fpga verilog FLASH write
Platform: | Size: 114688 | Author: zhongpeng | Hits:

[VHDL-FPGA-Verilog] ACTEL-FPGA-1602(Verilog)

Description: 1602液晶显示程序，用verilog写的！-1602 LCD program, written using verilog!
Platform: | Size: 4096 | Author: wns | Hits:

[Documents] 三角函数的Verilog HDL语言实现

Description: 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
Platform: | Size: 148480 | Author: 所罗门 | Hits:

[VHDL-FPGA-Verilog] UartRecv

Description: 利用FPGA实现简单的串口接收驱动程序，actel。(Using FPGA to implement a simple serial port receiver driver, Actel)
Platform: | Size: 338944 | Author: 苦瓜不苦 | Hits:

[Other] Actel8051Core

Description: Actel 8051 Verilog core
Platform: | Size: 428032 | Author: Dilogic | Hits:
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