Search - verilog of encoder

[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 45056 | Author: zs8292 | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] bch_encoder_decoder

Description: bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦-bch encoder+ decoder source code, Flash controller, communications are needed Oh
Platform: | Size: 136192 | Author: linchan | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[mpeg mp3] mp3encodec

Description: MP3编码器的设计，希望能给爱好MP3开发的朋友们带来帮助，多交流-MP3 encoder design, the development of hope that they will be MP3-loving friends to help bring about, more exchanges
Platform: | Size: 553984 | Author: 凡凡 | Hits:

[mpeg mp3] +++ANNEX_AB

Description: mp3编码器1，根据mp3标准编写，串行结构，c语言，具有比较好的可读性。-mp3 encoder 1, in accordance with the standard preparation of mp3, serial structure, c language, has a better readability.
Platform: | Size: 27648 | Author: libaiqsl | Hits:

[Other] 97_2D_2Level

Description: 這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder-This is a two-dimensional lift-style 9/7 discrete wavelet of Verilog source code, this is Encoder
Platform: | Size: 7728128 | Author: chiahao | Hits:

[VHDL-FPGA-Verilog] crc_verilog

Description: 循环码编码器verilog实现，里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Platform: | Size: 15360 | Author: 萍果 | Hits:

[Streaming Mpeg4] H.264

Description: 本书在介绍数字视频和视频编码的基本原理基础上，论述了H264的特点、编码器原理、解码器原理以及编解码器的实现方案。-This book, introducing digital video and video encoding based on the basic principles, discusses the characteristics of H264, encoder principle, the principle of the decoder and codec realization of the program.
Platform: | Size: 11018240 | Author: 许菀纯 | Hits:

[Other Embeded program] qep

Description: 一个QEP电路的verilog代码。输入信号是光电编码器的A相和B相信号和一个处理时钟，输出的是计数信号和方向信号。-A QEP circuit Verilog code. Input signal is the optical encoder of the A phase and B and believe that a deal with the clock, the output is the count signal and direction signal.
Platform: | Size: 1024 | Author: 张洁 | Hits:

[VHDL-FPGA-Verilog] crc_16

Description: 利用verilog实现的一个（2,1,2）卷积码的编码器,很有用的哟!-Verilog realize the use of a (2,1,2) convolutional code encoder, yo useful!
Platform: | Size: 1024 | Author: 刘横 | Hits:

[Wavelet] compressVLSI

Description: 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-High-speed image compression encoder the structural design of VLSI Research. Kdh quite the level of doctoral dissertation. Which describes in detail how to design the structure of wavelet transform VLSI. Verilog hdl design and structure of the assessment
Platform: | Size: 1733632 | Author: 黄辉 | Hits:

[VHDL-FPGA-Verilog] abs_code

Description: 这是用CPLD开发的读取绝对式编码器反馈的信号的代码，读取电机的转子的绝对位置和判断转动方向对于电机控制很实用。-This is read by the CPLD Development absolute encoder feedback signal to the code, read the motor' s rotor position and to determine the absolute direction of rotation is very useful for motor control.
Platform: | Size: 1602560 | Author: dengzhaoyun | Hits:

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[ELanguage] rs-codec-8-4

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

[VHDL-FPGA-Verilog] bch_encoder_decoder

[VHDL-FPGA-Verilog] DCT

[mpeg mp3] mp3encodec

[mpeg mp3] +++ANNEX_AB

[Other] 97_2D_2Level

[VHDL-FPGA-Verilog] crc_verilog

[Streaming Mpeg4] H.264

[Other Embeded program] qep

[VHDL-FPGA-Verilog] crc_16

[Wavelet] compressVLSI

[VHDL-FPGA-Verilog] abs_code

[VHDL-FPGA-Verilog] reedsolomon

[VHDL-FPGA-Verilog] 11FIRfliter

[VHDL-FPGA-Verilog] JPEG2000

[Other] rsencoder_latest.tar

[VHDL-FPGA-Verilog] viterbi

[VHDL-FPGA-Verilog] my_code

[VHDL-FPGA-Verilog] Program of 4 to 2 Encoder

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