Description: Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information. Platform: |
Size: 1887232 |
Author:ZY |
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Description: The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and verification of a digital UART (Universal
Asynchronous Receiver & Transmitter). Platform: |
Size: 141312 |
Author:ltrko9kd |
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Description: 51单片机IP核源码，可以在fpga实现，并进行仿真与验证-51 single-chip IP nuclear source, you can achieve the fpga, and simulation and verification Platform: |
Size: 67584 |
Author:xuhuifeng |
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Description: 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use Platform: |
Size: 194560 |
Author:雪晨 |
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Description: 一个很好的关于verilog的PPT
第1章 EDA设计与Verilog HDL语言概述
第2章 Verilog HDL基础与开发平台操作指南
第3章 Verilog HDL程序结构
第4章 VERILOG HDL语言基本要素
第5章 面向综合的行为描述语句
第6章 面向验证和仿真的行为描述语句
第7章 系统任务和编译预处理语句
第8章 VERILOG HDL可综合设计的难点解析
第9章 高级逻辑设计思想与代码风格
第10章 可综合状态机开发实例
第11章 常用逻辑的VERILOG HDL实现
第12章 XILINX硬核模块的VERILOG HDL调用
第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design Platform: |
Size: 27825152 |
Author:lyy |
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Description: verilog验证平台的使用
很不错 很详细 想具体-verilog verification platform is more like using a very good specific Platform: |
Size: 350208 |
Author:guoguo |
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Description: System Verilog for Verification, 2nd Edition.非常经典的资料，供IC开发的人员作自测平台或者验证的人员使用-System Verilog for Verification, 2nd Edition. Very classic information for IC self-test platform for the development of personnel for use by or verification Platform: |
Size: 1982464 |
Author:linhaidu |
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Description: Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book Platform: |
Size: 8890368 |
Author:鲁智深 |
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Description: IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE
Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a
standard textual format for a variety of design tools, including verification simulation, timing analysis, test
analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language
of choice by an overwhelming number of IC designers.
Platform: |
Size: 2200576 |
Author:adam |
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Description: verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process Platform: |
Size: 578560 |
Author:ni husheng |
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Description: 《设计与验证-Verilog HDL》，很好的一本FPGA程序员用书，讲解很是详细，非常实用-" Design and Verification-Verilog HDL" , a very good one FPGA programmer with the book, to explain very detailed, very practical Platform: |
Size: 12794880 |
Author:qihongye |
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Description: 其主要使用verilog编写fft程序主体，之后通过quartus和matlab实现对fft程序的测试，可以很好做到自动化验证(The main use of verilog prepared fft main program, and then achieved by quartus and matlab fft program testing, you can do a good job of automated verification) Platform: |
Size: 995328 |
Author:未曾走远 |
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Description: Material to learn how to use system verilog and how to write testbenches for verification. Platform: |
Size: 2763776 |
Author:DRAGON2018 |
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