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[VHDL-FPGA-Verilog] adpll

Description: 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
Platform: | Size: 2048 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Platform: | Size: 16772096 | Author: allen-haha | Hits:

[VHDL-FPGA-Verilog] VCO

Description: 压控振荡器的FPGA实现，Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
Platform: | Size: 1024 | Author: 法克尤 | Hits:

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