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[VHDL-FPGA-Verilogusb_funct

Description: usb1.0的核,有详细的usb核的设计源码,用verilog语言编写,同时附有相关的设计文档,质量不错-usb1.0 nuclear, nuclear usb detailed design source, using Verilog language, along with documents related to the design, quality good
Platform: | Size: 214016 | Author: | Hits:

[USB developusb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
Platform: | Size: 212992 | Author: 高杰 | Hits:

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