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[Other resource] usb_verilog.tar

Description: 文件包含一个usb 专用集成电路设计项目，用的verilog 原码-document contains a usb ASIC design, the original code verilog
Platform: | Size: 197240 | Author: jockeyhao | Hits:

[VHDL-FPGA-Verilog] usb1_funct

Description: usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
Platform: | Size: 52224 | Author: liuzefu | Hits:

[VHDL-FPGA-Verilog] usb_verilog.tar

Description: 文件包含一个usb 专用集成电路设计项目，用的verilog 原码-document contains a usb ASIC design, the original code verilog
Platform: | Size: 197632 | Author: jockeyhao | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
Platform: | Size: 212992 | Author: 高杰 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo用Verilog hdl的实现，这是一个比较常用的源码，文档中有很详细的注释，初学者应该可以看懂。-implementation using Verilog hdl usb, this is a common source, the document had a very detailed notes, beginners should understand.
Platform: | Size: 6144 | Author: zhulyan580086 | Hits:

[VHDL-FPGA-Verilog] Verilog_USB_OUT

Description: USB out，使用Verilog写的，包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document，USB firmware
Platform: | Size: 1153024 | Author: 严刚 | Hits:

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