Search - usb core

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[Other resource] USB 2.0 IP Core DL : 1: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Date : 2008-10-13 Size : 177.03kb User : 林风
[WEB Code] USB-shujucaiji DL : 0: USB数据采集系统论文-自己的毕业设计论文，花了很长时间做的，内容十分详细，包括核心代码和开发环境的设置。-USB Data Acquisition System papers-their graduation thesis design, and having spent a very long time. which is very detailed, including the core code and development environment configuration.
Date : 2008-10-13 Size : 123.02kb User : 安帝
[USB develop] usb20_ipcore_usb_funct DL : 0: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Date : Size : 204kb User : road
[ARM-PowerPC-ColdFire-MIPS] usbspeed DL : 0: USB core stack for the built-in USB device of LPC214x
Date : Size : 223kb User : hk
[Other Embeded program] usb-device-core-project-1.3-iar5-at91sam7se-ek DL : 0: ATmel的AT91sam7SE芯片 USB固件开发源代码-Atmel USB chip AT91sam7SE the source code for firmware development
Date : Size : 539kb User : 邵春伟
[USB develop] usb DL : 0: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Date : Size : 6kb User : polito
[SCM] STM32-USB DL : 0: 意法基于arm-contex内核的单片机的usb固件程序库-ST arm-contex-based MCU core usb firmware library
Date : Size : 956kb User : cxj
[ARM-PowerPC-ColdFire-MIPS] at91sam9263-ek-usb-all DL : 0: at91sam9263-ek板usb开发全套资料（包括iar、keil、gun工程）同时拥有ac97、ccid、cdc-serial、cdchid、cdcmsd、hidmsd、core、hid-keyboard、hid-mouse、hid-transfer、massstorage工程-at91sam9263-ek board usb develop a full set of data (including iar, keil, gun works) have both ac97, ccid, cdc-serial, cdchid, cdcmsd, hidmsd, core, hid-keyboard, hid-mouse, hid-transfer, massstorage Engineering
Date : Size : 11.29mb User : 文建祥
[USB develop] xapp997 DL : 0: xapp997 from xilinx, not so easy to find: an USB application for the Logicore USB core
Date : Size : 1.62mb User : bugidan
[Embeded Linux] Linux_USB_HUB_EHCI_COER.tar DL : 0: linux USB core ,usb hub,usb EHCI 讲解，学习USB框架和linux USB 源码不可缺少的文档。-linux USB core, usb hub, usb EHCI explain, learning linux USB source USB framework and an indispensable document.
Date : Size : 6.76mb User : feilong
[Other Embeded program] USB DL : 0: Workbench 5.30评估版软件利用上述开发软件，核心处理器采用基于Cortex-M3核的LPC1700芯片外围USB调试程序。直接打开工程文件就可轻松实现调试-Workbench 5.30 evaluation version of the software development using the above software, the core Cortex-M3 processor core based on the LPC1700 chip external USB debugger. Can directly open the project file for easy debugging
Date : Size : 1.34mb User : huyouchang
[VHDL-FPGA-Verilog] usb DL : 0: USB完整代码包括vhdl和verilog两种-usb ip core
Date : Size : 254kb User : 王强
[USB develop] usb DL : 0: usb core driver usb host驱动 -usb core driver usb host驱动
Date : Size : 85kb User : richie
[USB develop] USB DL : 0: crotex-M3内核的单片机的USB驱动，从实际入手，程序很明了，很容易就可以看明白。上机就能用-crotex-M3 microcontroller core, USB drive, the actual start, the program is very clear, very easy to see to understand. The machine can be used
Date : Size : 2.63mb User : 廖红财
[Linux-Unix] LinuxUSB-Core DL : 0: Linux那些事之我是USB Core， Linux那些事之我是USB Core-My thing is that Linux USB Core, Linux My thing is that USB Core
Date : Size : 1.08mb User : scorpio
[VHDL-FPGA-Verilog] verilog-usb--protel-design DL : 1: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Date : Size : 52kb User : 唐明桂
[USB develop] USB-1.1-IP-CORE-VHDL DL : 0: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Date : Size : 416kb User : sxhfjgl010
[Driver Develop] USB-Skeleton-program DL : 0: 提供了一个最基础的USB驱动程序，即USB骨架程序，可被看做一个最简单的USB设备驱动实例。 usb类驱动的信息,为了从usb核心得到一个次设备号,并取得注册的核心设备驱动- provides a the most fundamental of the USB driver, namely USB skeleton program can be regarded as one of the most simple USB device driver examples. Usb class driver info in order to get a minor number from the usb core,and to have the device registered with the driver core
Date : Size : 4kb User : 黄晓
[Technology Management] usb-architecture-in-linux DL : 0: 介绍linux下的usb架构,包括控制器模块/hub模块/usb core/设备功能部分-Introduced under linux usb architecture, including the controller module/hub module/usb core/equipment functional part
Date : Size : 218kb User : mengfandong
[Documents] pg137-axi-usb2-device(xilinx USB ip core) DL : 0: xilinx USB ip 核使用说明文档，接口完全和usb3320接口一致(Xilinx USB IP core usage instructions document, the interface is completely consistent with the usb3320 interface)
Date : Size : 700kb User : 黄国锋

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