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Description: iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
Platform: |
Size: 889991 |
Author: benny |
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Description: iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
-IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
Platform: |
Size: 889856 |
Author: benny |
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Description: This file provides an 8051 external data memory bus interface
for CoolRunner CPLDs. This file contains the state machine to
interface on the 8051 bus as well as the address registers, the address
decode logic, and example control registers, status registers, data input
registers, and data output registers. Interrupt logic is also included.
Note that this code should be modified to meet the requirements of the
system.
-This file provides an 8051 external data memory bus interface
for CoolRunner CPLDs. This file contains the state machine to
interface on the 8051 bus as well as the address registers, the address
decode logic, and example control registers, status registers, data input
registers, and data output registers. Interrupt logic is also included.
Note that this code should be modified to meet the requirements of the
system.
Platform: |
Size: 4096 |
Author: alex |
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Description: This code implements the control of the i2c bus with a MC68000 type interface. It is modeled from the M-bus component in certain Motorola uC. The I2C control is done in the component i2c_control and the uC interface is implemented in the component uC_interface. This file does not contain any logic descriptions, it simply instantiates the two components and hooks them together.
Platform: |
Size: 3072 |
Author: quantum_dot |
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Description: Xilinx提供的I2C控制器代码,Master/Slave全功能-
Readme File for I2C Customer Pack
Created: 7/8/99 ALS
Revised: 11/4/99 ALS
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File Contents
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This zip file contains the following folders:
\doc -- Document for the CoolRunner I2C Controller.
\exemplar -- Exemplar synthesis files. This design was synthesized using Exemplar
and the resulting EDIF file imported into XPLA Professional V3.22
\vhdl_source -- Source VHDL files:
i2c.vhd - top level file
i2c_control.vhd - control function for the I2C master/slave
shift.vhd - shift register
uc_interface.vhd- uC interface f
Platform: |
Size: 150528 |
Author: leon |
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Description: IIC总线微控制器的接口RTL代码（verilog）-the verilog code of IIC Uc_interface
Platform: |
Size: 3072 |
Author: 马凯英 |
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