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[ELanguage] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M yHDL cycle / bit accurate model * Synthesizable VHDL model
Platform: | Size: 154770 | Author: 鲁京 | Hits:

[Communication-Mobile] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Platform: | Size: 154624 | Author: | Hits:

[VHDL-FPGA-Verilog] turbocodes_latest.tar

Description: turbo encode and decoder
Platform: | Size: 83968 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] EnergyEfficientVLSIArchitectureforLinearTurboEqua

Description: Energy efficient for turbo encoder decoder
Platform: | Size: 536576 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] IterativeDecodingofBinary

Description: In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder.
Platform: | Size: 1515520 | Author: suresh | Hits:

[Program doc] 01316017

Description: investigating the performances and complexities of the various SISO algorithms. a turbo decoder with the selected SISO algorithm is designed and implemented using VHDL as design entry and simulation language
Platform: | Size: 239616 | Author: Gokhan | Hits:

[3G develop] turbocodes_latest.tar

Description: 基于sova算法的Turbo码解码VHDL工程文件，非常经典，包含Python高层仿真代码。-Turbo Decoder Release 0.3 MAIN FEATURES - * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model AUTHOR David Brochart <dbrochart@opencores.org>
Platform: | Size: 168960 | Author: John Smith | Hits:

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