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[Other resource] time24

Description: 用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
Platform: | Size: 321901 | Author: 许的开 | Hits:

[Applications] bank Simulation

Description: 银行的简易存储系统-banks simple storage systems
Platform: | Size: 1712128 | Author: 吴胜 | Hits:

[VHDL-FPGA-Verilog] time24

Description: 用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
Platform: | Size: 321536 | Author: 许的开 | Hits:

[VHDL-FPGA-Verilog] time12

Description: Program demonstrate time24 to time12 object conversion.
Platform: | Size: 1024 | Author: Strikerr | Hits:

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