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Description: This an example of simple RISC CPU implemented in SystemC.-This is an example of simple RISC CPU implemented in SystemC.
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Size: 41984 |
Author: R Zhang |
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Description: 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.
The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.
The simulator exhibits performance over 500 K instructions/sec, which is fairly high for a cycle-accurate system-level simulator.
The simulator’s source co
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Size: 4886528 |
Author: Archie |
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Description: SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
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Size: 47104 |
Author: lvpw |
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Description: systemC模仿RISC CPU的简单功能-system C foumulate the simple function of RISC CPU
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Size: 6035456 |
Author: 安延文 |
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Description: systemC模仿RISC CPU的一般功能-systemC imitate RISC CPU' s general functions
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Size: 6130688 |
Author: 安延文 |
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Description: systemC模仿RISC CPU的完全功能，包括时序，信号-systemC imitate fully functional RISC CPU, including the timing, signal
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Size: 5943296 |
Author: 安延文 |
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