Description: systemC imitate fully functional RISC CPU, including the timing, signal
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File list (Check if you may need any files):
RiscCpuC\Debug\main.obj
........\.....\main.sbr
........\.....\RamIo.obj
........\.....\RamIo.sbr
........\.....\reset.obj
........\.....\reset.sbr
........\.....\RiscCpu.bsc
........\.....\RiscCpu.exe
........\.....\RiscCpu.ilk
........\.....\riscCPU.obj
........\.....\RiscCpu.pch
........\.....\RiscCpu.pdb
........\.....\riscCPU.sbr
........\.....\vc60.idb
........\.....\vc60.pdb
........\main.asp
........\main.cpp
........\RamIo.cpp
........\RamIo.h
........\reset.asp
........\reset.cpp
........\reset.h
........\riscCPU.cpp
........\RiscCpu.dsp
........\RiscCpu.dsw
........\riscCPU.h
........\RiscCpu.ncb
........\RiscCpu.opt
........\RiscCpu.plg
........\risccpuC.vcd
........\Debug
RiscCpuC
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