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[Other resource] ssram.tar

Description: implemention of ssran in VHDL
Platform: | Size: 1767 | Author: peng | Hits:

[Other resource] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114780 | Author: king.xia | Hits:

[Other resource] 256X8 SSRAM 建模仿真与综合

Description: 一篇关于ssram建模仿真的文献
Platform: | Size: 1116804 | Author: aiyutan | Hits:

[Video Capture] sram_verilog

Description: 告诉图形采集 verilog代码 很简单的 第一次发-tell graphics Acquisition Verilog code is very simple first grant
Platform: | Size: 222208 | Author: 徐常志 | Hits:

[VHDL-FPGA-Verilog] ssram.tar

Description: implemention of ssran in VHDL
Platform: | Size: 2048 | Author: | Hits:

[Other] GetprocessRam

Description: 该程序可以获取任意运行进程的内存使用信息以及页面文件使用，程序中包括一些加载窗体，创建数组测试。-the program can get the process running the arbitrary use of information and memory page document use, procedures include some loading windows, creating an array testing.
Platform: | Size: 25600 | Author: diy | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[Other Embeded program] altera_avalon_cy7c1380_ssram

Description: 关于altera的SRAM的读写控制IP代码，有兴趣的朋友可以下去-On the SRAM
Platform: | Size: 7168 | Author: liufanyu | Hits:

[VHDL-FPGA-Verilog] DE1_SD_Card_Audio

Description: SD卡操作模块，一个简单的sd卡使用实例-SD card operation module, a simple example of the use of sd cards
Platform: | Size: 1041408 | Author: 刘勇 | Hits:

[Communication-Mobile] SSRAMcontroller

Description: SSRAM控制器,vhdl实现并通过验证-ssram controller,implement by vhdl and complier
Platform: | Size: 2048 | Author: 陈磊 | Hits:

[Documents] Memory

Description: 存储器类型介绍:SSRAM SDRAM Flash Memory EEPROM EPROM-Memory Introduction
Platform: | Size: 8192 | Author: Kim Zeng | Hits:

[VHDL-FPGA-Verilog] AHB_SRRAM

Description: SSRAM with AHB bus interface source code
Platform: | Size: 205824 | Author: nan | Hits:

[VHDL-FPGA-Verilog] ssramWR

Description: SSRAM CY7C1383C的读写延时控制程序-CY7C1383C delay control procedures to read and write
Platform: | Size: 1024 | Author: 张金龙 | Hits:

[VHDL-FPGA-Verilog] mem_ctrl

Description: 老外写的通用的存储器控制核，支持SDRAM SSRAM FLASH,ROM等等 8个片选信号 支持RMW cycles最大可达9*64M Bytes的存储器容量-Written by foreigners universal memory controller core, support for SDRAM SSRAM FLASH, ROM, etc. 8 chip select signals support RMW cycles up to 9* 64M Bytes of memory capacity
Platform: | Size: 397312 | Author: lishufei | Hits:

[VHDL-FPGA-Verilog] vga_gui

Description: 在DE2开发板上实现，由于DE2中的SSRAM只有512K，所以640*480*3（byte）的显存是不够的显示结果是经缩放 后的效果，具体可修改Altera_UP_Avalon_Pixel_Buffer buffer模块中的相关代码。 我把代码移植到DE2-70上后，显示的就很正常了。-In the DE2 development board to achieve, due to the SSRAM DE2 only 512K, so 640* 480* 3 (byte) of memory is not enough to show that the result is scaled by the effect of specific Altera_UP_Avalon_Pixel_Buffer buffer module can modify the relevant code. I put code into DE2-70 on, the display of the normal for the.
Platform: | Size: 29208576 | Author: 张业 | Hits:

[VHDL-FPGA-Verilog] ssram

Description: 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
Platform: | Size: 1024 | Author: koo | Hits:

[VHDL-FPGA-Verilog] 71V25761_Verilog_99056.tar

Description: SSRAM Simulation Model
Platform: | Size: 8192 | Author: Richard Klein | Hits:

[VHDL-FPGA-Verilog] ssram-and-tesebench

Description: 实现一个256x8的同步静态存储器SSRAM，用硬件描述语言Verilog写的，同时谢了测试程序-it realized a 256x8 SSRAM,writen by Hardware description language Verilog ,and include the testbench.
Platform: | Size: 1024 | Author: 李柏祥 | Hits:

[VHDL-FPGA-Verilog] ssram

Description: ssram using VHDL code
Platform: | Size: 1970176 | Author: simyunsub | Hits:

[VHDL-FPGA-Verilog] SSRAM-to-NOR-Flash-Bridge

Description: nor flash（m29w128g）的读，写，擦出等操作，另一边是标准的SSRAM操作接口。--one port is nor flash interface，including the basic operation of nor flash（m29w128g）；the other one is standard ssram interface。
Platform: | Size: 3072 | Author: dajiang | Hits:
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