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[Software Engineering] sobel_filter

Description: implementation of SOBEL filter using FPGA board RC200 in handle-c
Platform: | Size: 4096 | Author: nishu | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] DE2_CCD_sobel

Description: verilog编写的适用于fpga的3x3模板sobel滤波-verilog fpga prepared for the 3x3 template sobel filter
Platform: | Size: 5596160 | Author: 彭青艳 | Hits:

[VHDL-FPGA-Verilog] sobel2

Description: 新的sobel算子的FPGA实现。使用verilog语言，并调试通过~-The sobel operator new FPGA implementation. Verilog language, and debugging through to
Platform: | Size: 356352 | Author: abrams | Hits:

[Graph program] sobel

Description: 在FPGA中，采用verilog HDL语言实现图像处理算法sobel，仿真实验通过-In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment
Platform: | Size: 6255616 | Author: zhouhui | Hits:

[VHDL-FPGA-Verilog] edge-detection1

Description: 基于FPGA开发环境，根据Sobel model算法，关于边缘检测的verilog代码。-the code of edge detection based on verilog.
Platform: | Size: 1024 | Author: Oscar | Hits:

[VHDL-FPGA-Verilog] DE2_70_D5M_LTM

Description: filtre de sobel sur fpga
Platform: | Size: 201728 | Author: jordra | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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