Search - sine vhdl

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[Other] CORDIC_VHDL

Description: 用cordic算法来实现求解正弦,余弦及反正切的FPGA实现原代码-CORDIC algorithm used to achieve the solution of sine, cosine and tangent of the FPGA to achieve the original code
Platform: | Size: 427008 | Author: 汤文森 | Hits:

[Algorithm] VHDL

Description: 此代码可产生正弦波、三角波、正斜率拨、负斜率波波、矩形波五种波形-This code can generate sine wave, triangle wave, the slope is allocated, the negative slope of the ball, five rectangular-wave waveform
Platform: | Size: 1024 | Author: 刘三平 | Hits:

[VHDL-FPGA-Verilog] sine

Description: chdl 64位计数器，利用mif格式文件产生正弦波。可以在fpga模拟正弦波-chdl 64 bit counter, using sine wave generated mif format. Sine wave can be simulated in FPGA
Platform: | Size: 268288 | Author: yyqdian | Hits:

[VHDL-FPGA-Verilog] sinwave

Description: 正弦波信号发生的源码，有详细文档说明在quartus上创建工程到仿真、下载的步步操作-Sine wave signal source, has detailed documents created in the Quartus simulation works, download the step-by-step operation
Platform: | Size: 2471936 | Author: benyue | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
Platform: | Size: 9216 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
Platform: | Size: 675840 | Author: zzwuyu | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] daout-Sine-wave

Description: 正弦波的vhdl输出，使用VHDL编写的，已经通过调试-Sine wave output of the VHDL, the use of VHDL prepared already through debugging
Platform: | Size: 585728 | Author: zhang | Hits:

[Other] Sine

Description: 正弦波发生器，可以让大家学习正弦多种产生方法，可以设计具体电路-Sine wave generator, allowing them to learn the method for multiple sinusoidal, can design a specific circuit
Platform: | Size: 1028096 | Author: 秦寅 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
Platform: | Size: 1024 | Author: chenyubin | Hits:

[SCM] Sine

Description: 标准正弦信号发生器,并且含有正弦表,对于新手有些帮助-Standard sinusoidal signal generator, and contain sinusoidal form, and some help for novice
Platform: | Size: 2530304 | Author: 张金斗 | Hits:

[VHDL-FPGA-Verilog] DDS_FINAL

Description: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
Platform: | Size: 437248 | Author: Raju Kumar | Hits:

[VHDL-FPGA-Verilog] sine_wave_generator_using_FPGA_implementation

Description: 该资料介绍了用FPGA实现正弦波发生器，原理是利用内置rom表，通过查询的方式实现输出，然后经过外部DAC输出，频率达到1MHz-The information on the sine wave generator using FPGA implementation, the principle is the use of built-in rom form, by querying the means to achieve the output, and then an external DAC output frequency of 1MHz
Platform: | Size: 2190336 | Author: 陈振林 | Hits:

[VHDL-FPGA-Verilog] Sinewave

Description: vhdl code for sine wave generator
Platform: | Size: 1024 | Author: Sreekumar Sreenivas | Hits:

[VHDL-FPGA-Verilog] invsinwave

Description: vhdl code for inverse sine wave.
Platform: | Size: 1024 | Author: Sreekumar Sreenivas | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 利用VHDL实现任意函数发生器，包括方波、正弦波、三角波等。-The use of VHDL to achieve arbitrary function generator, including square, sine wave, triangle wave and so on.
Platform: | Size: 39936 | Author: 陈海巍 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: ROM型正弦信号发生器，从rom中读取正弦波的点，循环输出，经AD生成波形，环境为quartus-sine generator in quartus
Platform: | Size: 677888 | Author: 张文 | Hits:

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[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

[assembly language] sine

[Other] CORDIC_VHDL

[Algorithm] VHDL

[VHDL-FPGA-Verilog] sine

[VHDL-FPGA-Verilog] sinwave

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] sine-generator

[VHDL-FPGA-Verilog] VHDL-ROM4

[VHDL-FPGA-Verilog] daout-Sine-wave

[Other] Sine

[VHDL-FPGA-Verilog] VHDL

[SCM] Sine

[VHDL-FPGA-Verilog] DDS_FINAL

[VHDL-FPGA-Verilog] sine_wave_generator_using_FPGA_implementation

[VHDL-FPGA-Verilog] Sinewave

[VHDL-FPGA-Verilog] invsinwave

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] sine-generator

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