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Description: 使用FPGA做SDRAM控制器 -SDRAM controller using FPGA so
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Size: 357376 |
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Description: verilog 写的 memory controller ,可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
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Size: 331776 |
Author: youjia |
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Description: sdram的详细介绍,详细介绍了sdram的存储机制,以及操作时序-A detailed description of SDRAM, detailing SDRAM memory mechanisms, as well as the operation timing
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Size: 704512 |
Author: 陈华 |
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Description: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief
description of each sub-section. The design consists of:
· PowerPC processor
· PLB-OPB bridge
· BlockRAM Memory Controller
· SDRAM Controller
· Two GPIO ports
· A UART Port
· External SDRAM-SDRAM reference design: mainly include The following figure shows a high-level block diagram for this reference design followed by a briefdescription of each sub-section. The design consists of: PowerPC processor PLB-OPB bridge BlockRAM Memory Controller SDRAM Controller Two GPIO ports A UART Port External SDRAM
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Size: 33792 |
Author: 庞志勇 |
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Description: sdram操作的vhdl源代码,对自己编写SDRAM核有很好的参考意义-SDRAM operation of VHDL source code, the preparation of their own nuclear SDRAM have a good reference value
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Size: 2048 |
Author: 宋军 |
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Description: SDRAM控制IP核的VHDL语言源代码,需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
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Size: 88064 |
Author: 周华茂 |
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Description: s3c2440的方案包括sdram 网络等protel格式-The program includes S3C2440 SDRAM networks Protel format
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Size: 125952 |
Author: ydd |
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Description: The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.-err
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Size: 2628608 |
Author: ronsullivan |
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Description: 44B0嵌入式系统设计与开发
完整的原理图,包括Etc,FLASH,jtag_sch,Sdram-44B0 embedded system design and development of a complete schematic diagram, including Etc, FLASH, jtag_sch, Sdram
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Size: 238592 |
Author: 胡正明 |
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Description:
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Size: 35840 |
Author: 郭红梅 |
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Description: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
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Size: 777216 |
Author: 黄辉辉 |
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Description: ADI-BF533 DSP的启动初始化配置源代码-ADI-BF533 DSP startup to configure the source code to initialize
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Size: 434176 |
Author: wdz |
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Description: 这是我学USB时候,在写的s3c2410上实现的一个32M的优盘演示程序。因为主要目的是在学习USB协议,所以U盘的文件内容直接以SDRAM作为存储介质。-This is my USB school when S3C2410 written on a 32M realize the USB demo program. Because the main purpose is to learn from USB protocol, so the contents of the paper U disk directly to SDRAM as storage medium.
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Size: 129024 |
Author: peizhiluo |
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Description: ALTERA SDR AM Controller White Paper
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Size: 658432 |
Author: 付茗 |
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Description: SDRAM的逻辑Bank与芯片容量表示方法.-SDRAM chip logic Bank with the capacity of representation.
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Size: 1153024 |
Author: 李飞 |
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Description: SDRAM控制模块;图象采集系统说明性稳当;DSP图象采集系统。SDRAM作为存储器。-SDRAM control module image acquisition system illustrative trustworthy DSP image acquisition system. SDRAM as the memory.
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Size: 179200 |
Author: yan |
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Description: SDRAM控制器的设计与VHDL实现
是pdf格式的。在工程中实现过-SDRAM Controller Design with VHDL realize is pdf format. In the projects implemented
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Size: 138240 |
Author: hjx |
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Description: DSP tms320c6713 的EMIF 配置gel文件例子,按此配置DSP能访问外部SDRAM和FLASH,已经过验证。-DSP tms320c6713 the EMIF configuration file example gel, this DSP can configure access to external SDRAM and FLASH, has already been verified.
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Size: 3072 |
Author: 鲍亚其 |
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Description: SDRAM的读写测试,便于大家深入了解SDRAM的工作原理!-SDRAM read and write tests for our in-depth understanding of the working principle of SDRAM!
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Size: 156672 |
Author: 张文 |
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Description: 8读8写SDRAM verilog 程序-8 Reading SDRAM verilog to write 8 procedures
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Size: 2091008 |
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