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[VHDL-FPGA-Verilogscaler

Description: VHDL描述的简易图像缩小模块,将PAL制720×576的图片缩小为512×410,采用最近临域法,13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Platform: | Size: 9216 | Author: wgy | Hits:

[VHDL-FPGA-Verilogvideo

Description:
Platform: | Size: 3486720 | Author: liao | Hits:

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