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[Communication] VisualBasic_comm

Description: 一个VB控制串口的实例，可以给利用VB基于RS232开发监控、设置等程序提供参考-VB control of a serial example, can use Visual Basic to develop based on the RS232 control, the procedures set up to provide reference
Platform: | Size: 4851712 | Author: 马建新 | Hits:

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] RS232

Description: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Platform: | Size: 2048 | Author: ronghy | Hits:

[Other] rs232

Description: this is a vhdl version of MiniUART implementation
Platform: | Size: 964608 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] RS422

Description: 这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试-This is a VHDL development with RS422 communication procedures, in the ALTERA FLEX EPF10K passed the test
Platform: | Size: 1586176 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] uart_v11

Description: uart串口的vhdl语言程序。本人调试过 ，非常好用-serial UART VHDL Language Program. I debug, and very easy to use
Platform: | Size: 43008 | Author: hjj | Hits:

[Com Port] serialrxtx

Description: 个人原创，已经测试通过。功能：完成串行数据与RS232格式数据的收发转换，ST16C450+串并双向转换兼收发时序产生功能，优点：省去了传统的ST16C450需要CPU干预的缺点，简化设计， 纯硬件自动转换，缺点：忽略各种异常报警，适用于误码测试时使用（传输错误由误码测试功能模块完成检测）。-Personal originality, have the test. Function: the completion of serial data and send and receive RS232 data format conversion, ST16C450+ String and two-way conversions and transceivers generate timing features, advantages: eliminating the traditional need for CPU intervention ST16C450 shortcomings, simplify the design, pure hardware automatically converted, disadvantages: ignore the various abnormal alarm, error test applies to the use of (transmission errors by the error detection test function modules completed).
Platform: | Size: 26624 | Author: fg0112 | Hits:

[Com Port] uart

Description: 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
Platform: | Size: 6144 | Author: zhangjiansen | Hits:

[Software Engineering] TopLevelRS232

Description: TopLevel Rs232 VHDL code
Platform: | Size: 1024 | Author: mohd | Hits:

[VHDL-FPGA-Verilog] uart01

Description: 一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序-A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure
Platform: | Size: 140288 | Author: ouping | Hits:

[Com Port] rxd

Description: VHDL语言写的UART通信接收端程序，适用于RS232协议-VHDL language the receiving end of the UART communication procedures, applicable to RS232 protocol
Platform: | Size: 2048 | Author: 刘红平 | Hits:

[Com Port] uart_zhiwen

Description: RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
Platform: | Size: 109568 | Author: zhangyi | Hits:

[Com Port] FPGArs232

Description: FPGA中实现rs232串口通信程序，上位机和FPGA互发数据-FPGA to achieve rs232 serial communication procedures, each host computer and FPGA-fat data
Platform: | Size: 100352 | Author: wg | Hits:

[VHDL-FPGA-Verilog] DM7_COLR_LCD_C5T

Description: 任意信号波形采样和频谱分析演示文件 ADC信号采样、RS232串行通信和频谱分析 增加ADC采样控制模块，接上ADC，即可把模拟信号采入PC机上显示，和相应的频谱分析。 -Arbitrary signal waveforms and spectral analysis of the sampling ADC signal sample presentation, RS232 serial communication and increase the ADC sampling frequency spectrum analysis control module, connected to ADC, the analog signal can take into the PC, display, and the corresponding spectral analysis.
Platform: | Size: 41984 | Author: 邢旭 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源-Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has been testing, it is a good resource
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[MiddleWare] mmu_uart

Description: uart RS232 VHDL Code
Platform: | Size: 18432 | Author: hype | Hits:

[VHDL-FPGA-Verilog] PS2andRS232

Description: 基于Verilog语言PS2接口和RS232接口的实现 有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
Platform: | Size: 1770496 | Author: generalj | Hits:

[VHDL-FPGA-Verilog] PS2RS232

Description: 这是关于PS2和rs232串口的代码，verilog的，是深入了解串口的好的学习实例。-good code about rs232 and ps2
Platform: | Size: 1770496 | Author: 秦天 | Hits:

[Com Port] RS232

Description: simple example for uart on fpga
Platform: | Size: 714752 | Author: Jay | Hits:
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