Search - risc 16

[Other resource] 16位16个精简指令RISC单片机IP

Description: 16位16个精简指令RISC单片机IP,对于想学习学习处理器内核、编写自己的微处理器的朋友有帮助。-16 bit RISC MCU IP with 16 ops,if you want to study how write your own MCU down,you can get help with it.
Platform: | Size: 4015 | Author: 吴文河 | Hits:

[VHDL-FPGA-Verilog] risc cpu

Description: 一个很好的16位cpu ip内核，用quartus写的
Platform: | Size: 5888 | Author: kingkoyan | Hits:

[VHDL-FPGA-Verilog] 16位16个精简指令RISC单片机IP

Description:
Platform: | Size: 4096 | Author: 吴文河 | Hits:

[Embeded Linux] rtlinux__doc(2)

Description: ARM?系列微处理器作为全球 16/32 位 RISC 处理器市场的领先者，在许多领域内得到了成功的应用。近年来，ARM 在国内的应用也得到了飞速的发展，越来越多的公司和工程师在基于 ARM 的平台上面开发自己的产品。 -ARM microprocessor family as a global 16/32 bit RISC processor market leader, in many areas has been successfully applied. In recent years, the ARM in the applications has been developed rapidly, a growing number of companies and engineers based on the ARM platform above and develop its own products.
Platform: | Size: 220160 | Author: 另壶葱 | Hits:

[VHDL-FPGA-Verilog] 16_risc_cpu

Description: 一个支持精简指令的16位的risc cpu，可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
Platform: | Size: 163840 | Author: 董 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[Other] ATmega128(L)_cn

Description: 高性能、低功耗的 AVR® 8 位微处理器 • 先进的 RISC 结构 – 133 条指令 – 大多数可以在一个时钟周期内完成 – 32 x 8 通用工作寄存器 + 外设控制寄存器 – 全静态工作 – 工作于16 MHz 时性能高达16 MIPS-High-performance, low power AVR ? 8-bit microcontroller
Platform: | Size: 2607104 | Author: 刘小丽 | Hits:

[VHDL-FPGA-Verilog] 16bit_cpu

Description: 16位的RISC_CPU，应该对大家有帮助-16 of RISC_CPU, everyone should have to help
Platform: | Size: 439296 | Author: ekin | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前对这16个数进行排序，从大到小放置在18到33的位置求出前16个数的平均数，放在34的位置基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码使用quartus编译 cpu中 alu的设计可作为课程设计的参考此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[Other] cputest

Description: 自己刚写的一个RISC的cpu，位宽16，主要是测试其中的逻辑，数据宽度是一位，可以很容易扩展-Writing just one of their own RISC the cpu, bit 16, are testing one of the main logic, data width, a, can be easily extended
Platform: | Size: 21504 | Author: myliu | Hits:

[Other] MANIK

Description: MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).-MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).
Platform: | Size: 3395584 | Author: hfayed | Hits:

[VHDL-FPGA-Verilog] zxcpu

Description: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Platform: | Size: 1076224 | Author: zhaoshu | Hits:

[VHDL-FPGA-Verilog] risc

Description: 16位cpu的各功能模块的源程序，经过FPGA仿真通过，希望能帮到你-16-bit cpu' s each functional module of the source, through the FPGA emulation by, hope you can help
Platform: | Size: 375808 | Author: 大成 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU-design

Description: 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the three basic test file and Modelsim simulation results.
Platform: | Size: 413696 | Author: yu | Hits:

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