Description: 16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the three basic test file and Modelsim simulation results.
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File list (Check if you may need any files):
RISC CPU design
...............\CPU Design.pdf
...............\Screenshot-1.png
...............\Screenshot-2.png
...............\Screenshot.png
...............\accum.v
...............\addr_decode.v
...............\adr.v
...............\alu.v
...............\clk_gen.v
...............\counter.v
...............\cpu.v
...............\datactl.v
...............\machine.v
...............\machinectl.v
...............\out_reg.v
...............\ram.v
...............\register.v
...............\rom.v
...............\t.v
...............\test result.txt
...............\test1.dat
...............\test1.png
...............\test1.pro
...............\test2.dat
...............\test2.png
...............\test2.pro
...............\test3.dat
...............\test3.png
...............\test3.pro
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