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[VHDL-FPGA-VerilogPN

Description: 利用vhdl语言编程实现的pn码产生.在quartus ii中通过-The use of VHDL language programming code generated realize the pn. Quartus ii adopted in
Platform: | Size: 90112 | Author: zhangtian | Hits:

[matlabpn_gen_vhd_211

Description: 通信中常用的PN序列产生器的源代码全部打包-Communications commonly used in PN sequence generator, the source code of all packaged
Platform: | Size: 129024 | Author: jinyong | Hits:

[VHDL-FPGA-Verilogpn_generator

Description: FPGA实现pn发生器,Verilog代码实现,另带modlesim的仿真测试文件,很有价值。-FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
Platform: | Size: 3072 | Author: 胡佳 | Hits:

[Software Engineeringpn

Description: pn码串并结合快速捕获算法的改进与研究,详细介绍了串并结合捕获算法的优点-pn code acquisition algorithm for strings in combination with rapid improvement and research, detailing the string combined with the advantages of capturing algorithm
Platform: | Size: 3381248 | Author: 员丽琼 | Hits:

[VHDL-FPGA-VerilogPN4

Description: 语言:VHDL 功能:该PN4序列的特点为将一个4位序列的前两位取异或,再让序列左移一位,用异或的结果作为序列的最后一位。序列周期是15,即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测,首先捕获相位。然后,规定测试的码的总个数,统计这些码中有多少个不能满足PN序列特点的,用计数器统计个数。如果发现误码过多,可能是相位失调,重新捕获相位,再进行误码检测。 仿真工具:modelsim 综合工具:quartus -Language: VHDL function: the sequence characteristics of the PN4 a 4-bit sequence of the first two to take different or, let a sequence of left, with the result as a sequence of different or the last one. Sequence cycle is 15, or 15-bit pseudo-random sequence. Including sequence generation module and detection module. For error detection, the first capture phase. Then, provided the total number of test code, statistics, the number of these codes can not meet the characteristics of PN sequences, with the number of counter statistics. If you find too many errors, it may be the phase offset, re-acquisition phase, then the error detection. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 4096 | Author: huangjiaju | Hits:

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