Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - pipelining

Search list

[Other resource] 能综合的YCrCb2RGB模块（verilog)_采用3级流水线

Description: 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
Platform: | Size: 1080 | Author: 于飞 | Hits:

[Windows Develop] MIPS

Description: 《MIPS五级整数流水线模拟系统》设计文档与源代码。 [代码性质] VC完整应用程序代码-The source and design document of <MIPS simulant system of 5 level int pipelining>. [code kind] VC whole application source code.
Platform: | Size: 992013 | Author: 毛建孟 | Hits:

[Windows Develop] MIPS

Description: 《MIPS五级整数流水线模拟系统》设计文档与源代码。 [代码性质] VC完整应用程序代码-The source and design document of <MIPS simulant system of 5 level int pipelining>. [code kind] VC whole application source code.
Platform: | Size: 992256 | Author: 毛建孟 | Hits:

[VHDL-FPGA-Verilog] 能综合的YCrCb2RGB模块（verilog)_采用3级流水线

Description: 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
Platform: | Size: 1024 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] bbb

Description: AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.
Platform: | Size: 216064 | Author: sss | Hits:

[Crack Hack] DES-pipeline

Description: 主要介绍算法的实现方式和流水线实现，而且有详细的原理介绍，推理，源码和仿真结果-The main way of introduction Algorithm and pipelining to achieve, but also has a detailed introduction of the principle, reasoning, source code and simulation results
Platform: | Size: 162816 | Author: 李佳 | Hits:

[Windows Develop] PipeLineNewVisual

Description: CPU内部流水线过程模拟程序，对其中各种状态进行模拟，并给出实时状态-CPU internal pipelining process simulation procedures, which simulate a variety of state, and gives real-time status
Platform: | Size: 69632 | Author: sjxyx | Hits:

[Software Engineering] DSP_TURBO

Description: 基于Log_MAP 算法, 提出了一种TURBO 码DSP 实现方案。利用内联函数、循环展开, 软件流水线技术对算法进行了优 化, 在TMS320C6416 芯片上实现了36Mbps 的编码速率及1.6Mbps 译码速率(5 次迭代)。该方案可以灵活设置码率、帧长、迭 代次数等关键参数, 适用于不同要求的高速通信系统-Log_MAP based algorithms, a DSP to achieve the program TURBO code. The use of inline functions, the cycle started, the software pipelining algorithm is optimized, in the TMS320C6416 chip has been realized in the encoding rate of 36Mbps and 1.6Mbps decoding rate (5 iterations). The program can be set bit-rate flexibility,帧长, iterative frequency of key parameters, applicable to the different requirements of high-speed communication system
Platform: | Size: 488448 | Author: ynhuyong | Hits:

[Crack Hack] 3DES_FPGA

Description: 介绍了3DES加密算法的原理并详尽描述了该算法的FPGA设计实现。采用了状态机和流水线技术，使得在面积和速度上达到最佳优化；添加了输入和输出接口的设计以增强该算法应用的灵活性。各模块均用硬件描述语言实现，最终下载到FPGA芯片Stratix EP1S25F780C5中。-3DES encryption algorithm, introduced the principle and detailed description of the FPGA algorithm design. Use of state machine and pipelining technology, makes the size and speed to achieve the best optimization added input and output interface design to enhance the flexibility of the application of the algorithm. Each module are used hardware description language to achieve, and ultimately downloaded to the FPGA chip in Stratix EP1S25F780C5.
Platform: | Size: 159744 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。 因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[Internet-Network] w3c-libwww-5.4.0

Description: www工具包. 这是W3C官方支持的www支撑库. 其中提供通用目的的客户端的WebAPI: complete HTTP/1.1 (with caching, pipelining, PUT, POST, Digest Authentication, deflate, etc), MySQL logging, FTP, HTML/4, XML (expat), RDF (SiRPAC), WebDAV, and much more-Libwww is a highly modular, general-purpose client side Web API written in C for Unix and Windows (Win32). It s well suited for both small and large applications, like browser/editors, robots, batch tools, etc. Pluggable modules provided with libwww include complete HTTP/1.1 (with caching, pipelining, PUT, POST, Digest Authentication, deflate, etc), MySQL logging, FTP, HTML/4, XML (expat), RDF (SiRPAC), WebDAV, and much more. The purpose of libwww is to serve as a testbed for protocol experiments.
Platform: | Size: 1688576 | Author: Banlyst Yeh | Hits:

[Software Engineering] FPGA

Description: 流水线技术在FPGA设计中的应用 pdf -Pipelining Technology in FPGA Design
Platform: | Size: 78848 | Author: gigi | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧-About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
Platform: | Size: 1028096 | Author: JET | Hits:

[Other] 11

Description: NCO 在信号处理方面有着广泛的应用。而函数发生器是NCO 中的关键部分，本文基 于FPGA 用状态机和流水线方法实现了CORDIC 算法，并取代了传统的ROM 查找表法。 最后通过Quartus II 软件给出仿真结果，验证了理论的正确性。-NCO in the Signal Processing has a wide range of applications. The function generator is a critical part of NCO, the paper-based FPGA using state machine implementation of the Ways and pipelining CORDIC algorithm, and replaces the traditional ROM look-up table method. Finally through the Quartus II software give simulation results to verify the correctness of the theory.
Platform: | Size: 164864 | Author: LEO | Hits:

[Other] erweiDCT

Description: 用 FPGA实现了二维离散余弦变换和逆变换，结构设计采用行列分解法，乘法器采用移位求和的方法实现，并且采用流水线结构设计，提高处理核的性能-Using FPGA to achieve the two-dimensional discrete cosine transform and inverse transform, the structural design of the use of the ranks of decomposition, the sum of multipliers using displacement method, and the structural design of the use of pipelining to improve the performance of the disposal of nuclear
Platform: | Size: 129024 | Author: 哈哈 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[VHDL-FPGA-Verilog] 09912007AEScoremodules

Description: aes description architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
Platform: | Size: 6144 | Author: tarang | Hits:

[Industry research] The-Impact-of-Wave-Pipelining-on-Future-Interconn

Description: The Impact of Wave Pipelining on Future Interconnect Technologies
Platform: | Size: 510976 | Author: cryptist | Hits:

[Industry research] Wave-Pipelining-A-Tutorial-and-Research-survey.zi

Description: Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wave-pipelining and a survey of wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits
Platform: | Size: 237568 | Author: cryptist | Hits:

[Other] Pipeline

Description: Labview FPGA code for pipelining
Platform: | Size: 108544 | Author: pandugundu | Hits:
« 12 3 4 »

CodeBus www.codebus.net