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[Other resource] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 809 | Author: qjyong | Hits:

[Other resource] leg_source

Description: verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
Platform: | Size: 656578 | Author: lumingzhi | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[ARM-PowerPC-ColdFire-MIPS] leg_source

Description: verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
Platform: | Size: 656384 | Author: lumingzhi | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: | Size: 3072 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] cordic

Description: cordic verilog 程序及仿真结果 8级流水线-cordic verilog simulation results procedures and eight lines
Platform: | Size: 1024 | Author: elisen | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[VHDL-FPGA-Verilog] mult_piped_8x8

Description: 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
Platform: | Size: 1024 | Author: 江浩 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_multi

Description: mips processor multicycle non-pipelined microprocessor by verilog
Platform: | Size: 9216 | Author: JACD | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips2

Description: fully working mips pipelined with all files
Platform: | Size: 55296 | Author: ramy | Hits:

[Crack Hack] tripledes

Description: 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
Platform: | Size: 31744 | Author: Yan, Like | Hits:

[VHDL-FPGA-Verilog] SinglecycleCPU

Description: 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
Platform: | Size: 26624 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] mult_addtree

Description: 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] pipe_mul8

Description: verilog实现的流水线8位乘法器，效率高，代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
Platform: | Size: 486400 | Author: flier | Hits:

[VHDL-FPGA-Verilog] Fast-adder-design-using-verilog

Description: 用Verilog设计各种快速加法器（四位先行进位加法器、选择进位加法器、流水线加法器）-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
Platform: | Size: 941056 | Author: zhxuqin | Hits:

[Other] pipelined-CPU

Description: verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
Platform: | Size: 7625728 | Author: 黄晓颖 | Hits:

[VHDL-FPGA-Verilog] 8-point-pipeline-fft-by-verilog.pdf

Description: 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog
Platform: | Size: 220160 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] CPU_Verilog

Description: 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
Platform: | Size: 12288 | Author: fairchildfzc | Hits:

[VHDL-FPGA-Verilog] e55_mul_addtree

Description: 实现4位乘法器的流水线操作计算，便于理解流水线(The implementation of pipelined operation of 4 bit multiplier is convenient for understanding pipelining)
Platform: | Size: 105472 | Author: yuanjingwei | Hits:
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