Search - pipeline cordic

[ActiveX/DCOM/ATL] CORDIC_ip

Description: cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v r : Cordic Mode. r = Rotation, v = Vectoring 32 : Precision of the individual vector components. 16 : Precision of the angle. 12 : Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: | Size: 458196 | Author: abcoabco | Hits:

[ActiveX/DCOM/ATL] CORDIC_ip

Description: cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v r : Cordic Mode. r = Rotation, v = Vectoring 32 : Precision of the individual vector components. 16 : Precision of the angle. 12 : Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: | Size: 457728 | Author: abcoabco | Hits:

[VHDL-FPGA-Verilog] cordic

Description: vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
Platform: | Size: 1024 | Author: lmy | Hits:

[VHDL-FPGA-Verilog] Cordic123

Description: for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
Platform: | Size: 109568 | Author: jai | Hits:

[VHDL-FPGA-Verilog] cordic_new

Description: Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation.-Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation. This original program can be seen in the book: digital processing with FPGA (Uwe Baese), the disadvantage is that the logic cells increases with iteration steps. You can also try this program using state machine instead of this pipeline.
Platform: | Size: 1024 | Author: 包一明 | Hits:

[VHDL-FPGA-Verilog] cordic_mpy_100722

Description: 6bit & 32 bit pipeline CORDIC 乘法器-6bit & 32 bit pipeline CORDIC Multiplier
Platform: | Size: 93184 | Author: 彭洪 | Hits:

[VHDL-FPGA-Verilog] cordic-verilog

Description: 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
Platform: | Size: 1024 | Author: 朱子翰 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
Platform: | Size: 1024 | Author: 郭良谦 | Hits:

[VHDL-FPGA-Verilog] cordic_atan

Description: 实现cordic vector模式 3级流水线 24级迭代-24 iterations of the three pipeline cordic vector mode
Platform: | Size: 3072 | Author: 呵呵呵 | Hits:

[Windows Develop] cordic

Description: verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
Platform: | Size: 1024 | Author: 刘大远 | Hits:

[Software Engineering] SINANDCOS-CORDIC

Description: 该资料是利用cordic算法实现正余弦函数计算输出的源程序及说明。资料中包含迭代算法和流水线算法。-This information is to use cordic algorithm source code and instructions cosine function calculates the output. Iterative algorithms and data contained in the pipeline algorithm.
Platform: | Size: 116736 | Author: chenjianwen | Hits:

[VHDL-FPGA-Verilog] Cordic-arithmetic-pipeline

Description: FPGA实现基于Cordic算法的流水线结构设计，相关verilog语言代码-FPGA to realize the Cordic code
Platform: | Size: 229376 | Author: 孙永林 | Hits:

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[ActiveX/DCOM/ATL] CORDIC_ip

[ActiveX/DCOM/ATL] CORDIC_ip

[VHDL-FPGA-Verilog] cordic

[VHDL-FPGA-Verilog] Cordic123

[VHDL-FPGA-Verilog] cordic_new

[VHDL-FPGA-Verilog] cordic_mpy_100722

[VHDL-FPGA-Verilog] cordic-verilog

[VHDL-FPGA-Verilog] cordic

[VHDL-FPGA-Verilog] cordic_atan

[Windows Develop] cordic

[Software Engineering] SINANDCOS-CORDIC

[VHDL-FPGA-Verilog] Cordic-arithmetic-pipeline

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