Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF Platform: |
Size: 124928 |
Author:于洪彪 |
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Description: 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.-Based on fuzzy logic control of digital phase-locked loop for the communication system in carrier recovery. Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system. Platform: |
Size: 33792 |
Author:gogomx |
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Description: 一个简单的锁相环matlab程序，可以很好的完成锁相功能-A simple phase-locked loop matlab program, you can complete a good lock function Platform: |
Size: 1024 |
Author:阎峰 |
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Description: PLECS是一个用于电路和控制结合的多功能仿真软件，尤其适用于电力电子和传动系统。这个PLECS模块是一个锁相环（这个软件没有自带锁相环），这个锁相环是照着MATLAB底层文件搭建的-PLECS is a versatile simulation software for circuit and control, especially for power electronics and transmission system. This PLECS module is a phase locked loop (this software does not own the PLL), this phase lock loop is built on the bottom of the MATLAB file Platform: |
Size: 10240 |
Author:赵彦锦 |
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Description: 编制Matlab仿真程
序。通过计算机仿真比较可以得出动态（捕获）性能，并画出改变某个参数条件下的响
应曲线，根据仿真结果更加直观、系统地分析环路的动态性能，为采样锁相环的研究和
工程设计提供参考。
-Through the computer simulation comparison can be obtained dynamic (capture) performance, and draw a change under a certain parameter conditions
According to the simulation results, the dynamic performance of the loop is systematically analyzed, and the research of the phase locked loop is studied.
Engineering design for reference. Platform: |
Size: 3072 |
Author:廖 |
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Description: Gardner位同步算法与锁相环的联合仿真程序.加入了时偏和频偏，能很好地锁定时偏和频偏，得到最佳采样输出。(Gardner bit synchronization algorithm and phase-locked loop joint simulation program, adding time offset and frequency offset, can well lock the bias and frequency offset, get the best sampling output.) Platform: |
Size: 2581504 |
Author:fan_xianbao
|
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