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Description: 这是一个perl程序
只需要在cmd中运行，参数为你的Verilog名字
功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------|
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#-----copyright(C) Xzmeng 2010-------------------------------|
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#Date:2010-12-18 21:55:48------------------------------------|
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#Run the pl followed with the verlog file name,such as aaa.v |
#Put the original verilog file(.v) in the current directory. |
#------------------------------------------------------------|
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#And you need to gurrantee that there is only one "input" or |
#"output" per line. |
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#------------------------------------------------------------|
Platform: |
Size: 2048 |
Author: zishan |
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