Search - parallel to serial vhdl

[Other] s2p

Description: 用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good
Platform: | Size: 99367 | Author: 国宝 | Hits:

[Other resource] bingzhuanchuan

Description: 这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
Platform: | Size: 1196 | Author: 华涛 | Hits:

[Other] s2p

Description: 用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good
Platform: | Size: 99328 | Author: 国宝 | Hits:

[VHDL-FPGA-Verilog] bingzhuanchuan

Description: 这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
Platform: | Size: 1024 | Author: 华涛 | Hits:

[VHDL-FPGA-Verilog] 080513154000

Description: 并行转串行的VHDL描述：基于FPGA的SPI发送模块的设计-Parallel to serial VHDL description: Based on the FPGA to send the SPI module
Platform: | Size: 95232 | Author: yaoqinghua | Hits:

[Windows Develop] parell_to_serial

Description: 该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。-The module main is completed and the string conversion functions. System_clk which is an input parallel clock frequency, it is the serial clock serial_clk eight times. byte_data_en is a parallel data input enable signal, byte_data is a parallel data input. serial_data is converted serial data, bit_data_enable is the serial data signal.
Platform: | Size: 1024 | Author: huangdecheng | Hits:

[Other] pie

Description: pie编码器,将串行数据并行输出的一种常用编码-pie encoder, parallel to serial data output of a common coding
Platform: | Size: 1024 | Author: bxy | Hits:

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

[Com Port] Receiver

Description: This file recieves the serial data from the UART and forward to Serial To Parallel module
Platform: | Size: 2048 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] signal_output

Description: 本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
Platform: | Size: 1160192 | Author: 蔡野锋 | Hits:

[VHDL-FPGA-Verilog] code

Description: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Platform: | Size: 5120 | Author: RUPA KRISHNA | Hits:

[VHDL-FPGA-Verilog] hh

Description: 串行输入并行输出用vhdl语言描述的有源代码主打色-Serial input parallel output using vhdl language to describe the main color of the source code
Platform: | Size: 1024 | Author: 吴越 | Hits:

[VHDL-FPGA-Verilog] P_to_ser

Description: parallel to serial data converter using VHDL
Platform: | Size: 98304 | Author: tg | Hits:

[Other] 91_WSS

Description: 实现窗口搜索算法的并行系统——序列存储器-Search algorithm to achieve the window parallel systems- Serial Memory
Platform: | Size: 2048 | Author: yeyang | Hits:

[VHDL-FPGA-Verilog] PISO

Description: this code is designed to perform parallel to serial operation it is very essential in every design
Platform: | Size: 161792 | Author: kimo | Hits:

[VHDL-FPGA-Verilog] PULSE

Description: 这是一个将6组并行数据串行输出的VHDL源码，配合外部电路可以输出正负脉冲，还附有逻辑图哦。-This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.
Platform: | Size: 7168 | Author: forget19 | Hits:

[VHDL-FPGA-Verilog] ps

Description: vhdl code to change the bits stream from parallel to serial
Platform: | Size: 1024 | Author: stevanus edwin | Hits:

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

Description: 用软件实现CRC校验码计算很难满足高速数据通信的要求，基于硬件的实现方法中，有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础，研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based implementations, there are classic serial algorithm LFSR, circuits and software algorithms derived from the other kinds of parallel computing. To the classic LFSR, circuit-based, study by the CRC byte parallel computing principles.
Platform: | Size: 205824 | Author: Geer | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[Education soft system] 2-bit-parallel-to-serial-conversion-VHDL-source-c

Description: This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion.
Platform: | Size: 1024 | Author: ss | Hits:

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[Other] s2p

[Other resource] bingzhuanchuan

[Other] s2p

[VHDL-FPGA-Verilog] bingzhuanchuan

[VHDL-FPGA-Verilog] 080513154000

[Windows Develop] parell_to_serial

[Other] pie

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

[Com Port] Receiver

[VHDL-FPGA-Verilog] signal_output

[VHDL-FPGA-Verilog] code

[VHDL-FPGA-Verilog] hh

[VHDL-FPGA-Verilog] P_to_ser

[Other] 91_WSS

[VHDL-FPGA-Verilog] PISO

[VHDL-FPGA-Verilog] PULSE

[VHDL-FPGA-Verilog] ps

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

[VHDL-FPGA-Verilog] vhdl-ad9910

[Education soft system] 2-bit-parallel-to-serial-conversion-VHDL-source-c

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