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Description: Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
Platform: | Size: 44553 | Author: 曹光明 | Hits:

[VHDL-FPGA-Verilog] news5f

Description: Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
Platform: | Size: 44032 | Author: 曹光明 | Hits:

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